A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained ind...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BURNS, DOUGLAS J, WILLIAMS, DOUGLAS D, HEYE, RICHARD, WITEK, RICHARD T, FENWICK, DAVID M, STAMM, REBECCA L, STANLEY, TIMOTHY J
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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