A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS

A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained ind...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BURNS, DOUGLAS J, WILLIAMS, DOUGLAS D, HEYE, RICHARD, WITEK, RICHARD T, FENWICK, DAVID M, STAMM, REBECCA L, STANLEY, TIMOTHY J
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BURNS, DOUGLAS J
WILLIAMS, DOUGLAS D
HEYE, RICHARD
WITEK, RICHARD T
FENWICK, DAVID M
STAMM, REBECCA L
STANLEY, TIMOTHY J
description A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0352633A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0352633A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0352633A33</originalsourceid><addsrcrecordid>eNrjZLB2VAjwDHD18fRzVfBwDPP0c1dw9FPw9AtxdQ9y9FFwdnT2cFVw8w9ScPb3DQgNcQ1SCAjyd3YNDvYPCuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAQbGpkZmxsaOxsZEKAEAa64osA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS</title><source>esp@cenet</source><creator>BURNS, DOUGLAS J ; WILLIAMS, DOUGLAS D ; HEYE, RICHARD ; WITEK, RICHARD T ; FENWICK, DAVID M ; STAMM, REBECCA L ; STANLEY, TIMOTHY J</creator><creatorcontrib>BURNS, DOUGLAS J ; WILLIAMS, DOUGLAS D ; HEYE, RICHARD ; WITEK, RICHARD T ; FENWICK, DAVID M ; STAMM, REBECCA L ; STANLEY, TIMOTHY J</creatorcontrib><description>A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.</description><edition>5</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1991</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19910417&amp;DB=EPODOC&amp;CC=EP&amp;NR=0352633A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19910417&amp;DB=EPODOC&amp;CC=EP&amp;NR=0352633A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BURNS, DOUGLAS J</creatorcontrib><creatorcontrib>WILLIAMS, DOUGLAS D</creatorcontrib><creatorcontrib>HEYE, RICHARD</creatorcontrib><creatorcontrib>WITEK, RICHARD T</creatorcontrib><creatorcontrib>FENWICK, DAVID M</creatorcontrib><creatorcontrib>STAMM, REBECCA L</creatorcontrib><creatorcontrib>STANLEY, TIMOTHY J</creatorcontrib><title>A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS</title><description>A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1991</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB2VAjwDHD18fRzVfBwDPP0c1dw9FPw9AtxdQ9y9FFwdnT2cFVw8w9ScPb3DQgNcQ1SCAjyd3YNDvYPCuZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAQbGpkZmxsaOxsZEKAEAa64osA</recordid><startdate>19910417</startdate><enddate>19910417</enddate><creator>BURNS, DOUGLAS J</creator><creator>WILLIAMS, DOUGLAS D</creator><creator>HEYE, RICHARD</creator><creator>WITEK, RICHARD T</creator><creator>FENWICK, DAVID M</creator><creator>STAMM, REBECCA L</creator><creator>STANLEY, TIMOTHY J</creator><scope>EVB</scope></search><sort><creationdate>19910417</creationdate><title>A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS</title><author>BURNS, DOUGLAS J ; WILLIAMS, DOUGLAS D ; HEYE, RICHARD ; WITEK, RICHARD T ; FENWICK, DAVID M ; STAMM, REBECCA L ; STANLEY, TIMOTHY J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0352633A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1991</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BURNS, DOUGLAS J</creatorcontrib><creatorcontrib>WILLIAMS, DOUGLAS D</creatorcontrib><creatorcontrib>HEYE, RICHARD</creatorcontrib><creatorcontrib>WITEK, RICHARD T</creatorcontrib><creatorcontrib>FENWICK, DAVID M</creatorcontrib><creatorcontrib>STAMM, REBECCA L</creatorcontrib><creatorcontrib>STANLEY, TIMOTHY J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BURNS, DOUGLAS J</au><au>WILLIAMS, DOUGLAS D</au><au>HEYE, RICHARD</au><au>WITEK, RICHARD T</au><au>FENWICK, DAVID M</au><au>STAMM, REBECCA L</au><au>STANLEY, TIMOTHY J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS</title><date>1991-04-17</date><risdate>1991</risdate><abstract>A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_EP0352633A3
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title A PIPELINE HAVING AN INTEGRAL CACHE FOR COMPUTER PROCESSORS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T10%3A10%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BURNS,%20DOUGLAS%20J&rft.date=1991-04-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0352633A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true