Analog macro embedded in a digital gate array
A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining...
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| creator | PETERSON, CLARENCE IVAN, JR DAVIS, JOHN DONALD MCCABE, SCOTT ALLAN PRITZLAFF, PHILIPP EDWARD, JR EWEN, JOHN FARLEY MOSLEY, JOSEPH MICHAEL NOTO, PHILIP KRANKIE MULLGRAV ALLAN LESLIE, JR CULICAN, EDWARD FRANCIS, SR |
| description | A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal. |
| format | Patent |
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| language | eng ; fre ; ger |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
| title | Analog macro embedded in a digital gate array |
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