MACRO STRUCTURAL ARRANGEMENT AND METHOD FOR GENERATING MACROS FOR VLSI SEMICONDUCTOR CIRCUIT DEVICES

A macro generation method and a macro structural arrangement are provided for a VLSI semiconductor circuit device (22). A circuit macro is defined by a plurality of circuit blocks including at least one control block (26) and an identified number of storage blocks (1-F). The control block includes a...

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Hauptverfasser:	AIPPERSPACH, ANTHONY GUS, DEWANZ, DOUGLAS MICHAEL, FITZGERALD, JOSEPH MICHAEL
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	AIPPERSPACH, ANTHONY GUS DEWANZ, DOUGLAS MICHAEL FITZGERALD, JOSEPH MICHAEL
description	A macro generation method and a macro structural arrangement are provided for a VLSI semiconductor circuit device (22). A circuit macro is defined by a plurality of circuit blocks including at least one control block (26) and an identified number of storage blocks (1-F). The control block includes a control section (32), a bit decoder section (34), a word decoder section (36) and a word selector section (38). Each of the storage blocks (28) includes a memory section (40), a bit selector section (42) and a sense, latch, driver section (44). One of a plurality of stored predetermined bit decoders is selectively provided for the bit decoder section. A required number of storage blocks is identified responsive to the selected bit decoder for the selected number of bits per word. A required number of word selectors and memory array subsections is identified responsive to the selected bit decoder for the selected number of words.
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A circuit macro is defined by a plurality of circuit blocks including at least one control block (26) and an identified number of storage blocks (1-F). The control block includes a control section (32), a bit decoder section (34), a word decoder section (36) and a word selector section (38). Each of the storage blocks (28) includes a memory section (40), a bit selector section (42) and a sense, latch, driver section (44). One of a plurality of stored predetermined bit decoders is selectively provided for the bit decoder section. A required number of storage blocks is identified responsive to the selected bit decoder for the selected number of bits per word. A required number of word selectors and memory array subsections is identified responsive to the selected bit decoder for the selected number of words.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	MACRO STRUCTURAL ARRANGEMENT AND METHOD FOR GENERATING MACROS FOR VLSI SEMICONDUCTOR CIRCUIT DEVICES
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