PROCESS FOR FORMING MOS INTEGRATED CIRCUIT DEVICES

A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Ligh...

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Hauptverfasser:	METZ, WERNER, ADAM, JR, SZLUK, NICHOLAS, JOHN, MILLER, GAYLE, WILBURN, MAHERAS, GEORGE
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	METZ, WERNER, ADAM, JR SZLUK, NICHOLAS, JOHN MILLER, GAYLE, WILBURN MAHERAS, GEORGE
description	A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Lightly doped extension of the source and drain regions are automatically formed by an LDD implant following an isotropic undercutting etch of the silicon. The process is readily adapted to optional guard band implants and other beneficial structures such as gate sidewall oxide spacers.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	PROCESS FOR FORMING MOS INTEGRATED CIRCUIT DEVICES
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