IMPROVED SILICON PACKAGES FOR POWER SEMICONDUCTOR DEVICES

A hermetically sealed package (24) for a power semiconductor wafer (22) is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer (22) such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap (32) and base (30), each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall (34) of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant (36) is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown betwen the cap and base. An arc suppressant (38) is disposed within the package between the semiconductor wafer edge and the sidewall for preventing electrical arcing between the base and cap.