LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LEDAK, PAUL JOSEPH, DEHOND, MITCHELL RAYMOND
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LEDAK, PAUL JOSEPH
DEHOND, MITCHELL RAYMOND
description
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0202535A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0202535A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0202535A33</originalsourceid><addsrcrecordid>eNrjZND3cYz0Dw1RCAjyd3YNDlZw8w9ScHYMdvZ3cVUI8_cJcXR3VQgO9wxx9lDw8Xf3dOZhYE1LzClO5YXS3AwKbq5AWd3Ugvz41OKCxOTUvNSSeNcAAyMDI1NjU0djYyKUAADBAiWM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC</title><source>esp@cenet</source><creator>LEDAK, PAUL JOSEPH ; DEHOND, MITCHELL RAYMOND</creator><creatorcontrib>LEDAK, PAUL JOSEPH ; DEHOND, MITCHELL RAYMOND</creatorcontrib><edition>4</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19891123&amp;DB=EPODOC&amp;CC=EP&amp;NR=0202535A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19891123&amp;DB=EPODOC&amp;CC=EP&amp;NR=0202535A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEDAK, PAUL JOSEPH</creatorcontrib><creatorcontrib>DEHOND, MITCHELL RAYMOND</creatorcontrib><title>LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC</title><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1989</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3cYz0Dw1RCAjyd3YNDlZw8w9ScHYMdvZ3cVUI8_cJcXR3VQgO9wxx9lDw8Xf3dOZhYE1LzClO5YXS3AwKbq5AWd3Ugvz41OKCxOTUvNSSeNcAAyMDI1NjU0djYyKUAADBAiWM</recordid><startdate>19891123</startdate><enddate>19891123</enddate><creator>LEDAK, PAUL JOSEPH</creator><creator>DEHOND, MITCHELL RAYMOND</creator><scope>EVB</scope></search><sort><creationdate>19891123</creationdate><title>LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC</title><author>LEDAK, PAUL JOSEPH ; DEHOND, MITCHELL RAYMOND</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0202535A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1989</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEDAK, PAUL JOSEPH</creatorcontrib><creatorcontrib>DEHOND, MITCHELL RAYMOND</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEDAK, PAUL JOSEPH</au><au>DEHOND, MITCHELL RAYMOND</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC</title><date>1989-11-23</date><risdate>1989</risdate><edition>4</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_EP0202535A3
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title LAYOUT PROCESS FOR CASCODE VOLTAGE SWITCH LOGIC
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T11%3A14%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEDAK,%20PAUL%20JOSEPH&rft.date=1989-11-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0202535A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true