TEST AND DIAGNOSTIC DEVICE FOR A DIGITAL CALCULATOR
The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the form of shift register means for the shift clock...
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Format: | Patent |
Sprache: | eng ; ger |
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