PIPELINED PROCESSOR HAVING DUAL CACHE MEMORIES

A pipelined digital computer processor system (10,) is provided comprising an instruction prefetch unit (IPU, 2) for prefetching instructions and an arithmetic logic processing unit (ALPU, 4) for executing instructions. The IPU (2) has associated with it a high speed instruction cache (6), and the A...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	THOMPSON, RICHARD F, WESTERFELD, ERIC C, QUEK, SWEE-MENG, DISNEY, DANIEL J
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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