Static memory cell having electrical elements on two levels
A static MOS memory device having a double polysilicon structure has parasitic transistors (Q5, Q6). The arrangement of electrical elements, transistors (Q1, Q2) and resistors (R1, R2), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic trans...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; ger |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | YAMAUCHI, TAKAHIKO |
| description | A static MOS memory device having a double polysilicon structure has parasitic transistors (Q5, Q6). The arrangement of electrical elements, transistors (Q1, Q2) and resistors (R1, R2), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic transistors (Q5, Q6) are maintained non-conductive regardless of the state of the memory cell, that is the state < > or < > of the cell, thereby avoiding an enhancement of memory cell current due to the presence of the parasitic transistors (Q5, Q6). Each parasitic transistor (Q5, Q6) has its gate electrode and source commonly connected. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP0146356A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP0146356A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP0146356A23</originalsourceid><addsrcrecordid>eNrjZLAOLkksyUxWyE3NzS-qVEhOzclRyEgsy8xLV0jNSU0uKcpMTswBMXNT80qKFfLzFErK8xVyUstSc4p5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakm8a4CBoYmZsamZo5ExEUoAWL8vEw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Static memory cell having electrical elements on two levels</title><source>esp@cenet</source><creator>YAMAUCHI, TAKAHIKO</creator><creatorcontrib>YAMAUCHI, TAKAHIKO</creatorcontrib><description>A static MOS memory device having a double polysilicon structure has parasitic transistors (Q5, Q6). The arrangement of electrical elements, transistors (Q1, Q2) and resistors (R1, R2), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic transistors (Q5, Q6) are maintained non-conductive regardless of the state of the memory cell, that is the state < > or < > of the cell, thereby avoiding an enhancement of memory cell current due to the presence of the parasitic transistors (Q5, Q6). Each parasitic transistor (Q5, Q6) has its gate electrode and source commonly connected.</description><edition>4</edition><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1985</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850626&DB=EPODOC&CC=EP&NR=0146356A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25555,76308</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850626&DB=EPODOC&CC=EP&NR=0146356A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAUCHI, TAKAHIKO</creatorcontrib><title>Static memory cell having electrical elements on two levels</title><description>A static MOS memory device having a double polysilicon structure has parasitic transistors (Q5, Q6). The arrangement of electrical elements, transistors (Q1, Q2) and resistors (R1, R2), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic transistors (Q5, Q6) are maintained non-conductive regardless of the state of the memory cell, that is the state < > or < > of the cell, thereby avoiding an enhancement of memory cell current due to the presence of the parasitic transistors (Q5, Q6). Each parasitic transistor (Q5, Q6) has its gate electrode and source commonly connected.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1985</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAOLkksyUxWyE3NzS-qVEhOzclRyEgsy8xLV0jNSU0uKcpMTswBMXNT80qKFfLzFErK8xVyUstSc4p5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakm8a4CBoYmZsamZo5ExEUoAWL8vEw</recordid><startdate>19850626</startdate><enddate>19850626</enddate><creator>YAMAUCHI, TAKAHIKO</creator><scope>EVB</scope></search><sort><creationdate>19850626</creationdate><title>Static memory cell having electrical elements on two levels</title><author>YAMAUCHI, TAKAHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP0146356A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>1985</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAUCHI, TAKAHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAUCHI, TAKAHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Static memory cell having electrical elements on two levels</title><date>1985-06-26</date><risdate>1985</risdate><abstract>A static MOS memory device having a double polysilicon structure has parasitic transistors (Q5, Q6). The arrangement of electrical elements, transistors (Q1, Q2) and resistors (R1, R2), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic transistors (Q5, Q6) are maintained non-conductive regardless of the state of the memory cell, that is the state < > or < > of the cell, thereby avoiding an enhancement of memory cell current due to the presence of the parasitic transistors (Q5, Q6). Each parasitic transistor (Q5, Q6) has its gate electrode and source commonly connected.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP0146356A2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | Static memory cell having electrical elements on two levels |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T19%3A53%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YAMAUCHI,%20TAKAHIKO&rft.date=1985-06-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP0146356A2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |