RANDOM ACCESS MEMORY ARRANGEMENT WITH A WORD REDUNDANCY SCHEME

A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the co...

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Bibliographische Detailangaben

Hauptverfasser:	KNEPPER, RONALD WILLIAM, PETROSKY, JOSEPH ANTHONY, JR, LUDLOW, PETER JASON
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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