CHIP CARRIER FOR LARGE SCALE INTEGRATED CIRCUITS AND A METHOD FOR THE FABRICATION OF THE CARRIER

A carrier for LSI (Large Scale Integration) chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip (11) with the plates (26, 46, 33) of the capacitor parallel to the chip mounting surface (9) or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments (26, 46) together to form the first one of the plates of a capacitor with the other plate (33) spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines (25, 45) which extend up to a severable link (24, 44) on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of th capacitor. Preferably, the structure includes a pair of parallel conductive charge redistribution planes (22, 35) above and below the capacitor plates with connections to the respective plates providing a low inductance structure achieved by providing a current distribution which results in cancellation of magnetic flux. The lower redistribution plane (35) is preferably connected directly to the lower capacitor plate (33). The upper redistribution plane (22) is preferably connected to the segments (26, 46) of the first capacitor plate by means of the vias (23, 25; 43, 45) which extend first to the chip mounting surface and then down to the redistribution plane which has connections (21) to the chip mounting pads (13).