HERSTELLUNGSMETHODE EINER INTEGRIERTEN SCHALTUNGSSTRUKTUR MIT LEITENDEN SCHICHTEN MIT GROSSER INNERER OBERFLÄCHE

An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techn...

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Hauptverfasser: VISOKAY, MARK, BASCERI, CEM, CUMMINGS, STEVEN D, GRAETTINGER, THOMAS M
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BASCERI, CEM
CUMMINGS, STEVEN D
GRAETTINGER, THOMAS M
description An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or "islanded" surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title HERSTELLUNGSMETHODE EINER INTEGRIERTEN SCHALTUNGSSTRUKTUR MIT LEITENDEN SCHICHTEN MIT GROSSER INNERER OBERFLÄCHE
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