PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN

An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further ele...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CLEVENGER, LARRY, WISE, MICHAEL, NARAYAN, CHANDRASEKHAR, HSU, LOUIS L, STEPHENS, JEREMY K
Format: Patent
Sprache:ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CLEVENGER, LARRY
WISE, MICHAEL
NARAYAN, CHANDRASEKHAR
HSU, LOUIS L
STEPHENS, JEREMY K
description An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE60132435TT2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE60132435TT2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE60132435TT23</originalsourceid><addsrcrecordid>eNqNi0EKwjAQRbtxIeodBveCWnUfm18TjINMJm5LkbgSLdT7YxUP4OrBe_-Pi-YcDBvx0UMU5EzYB3iFRJV01CR08krwDKFvYAum6CsHSXygxJYsYhyk-5wQwqDjBVIbJ-BpMbq19z7PfpwU8xpauUXunk3uu_aaH_nVWOyWq3K9Kbeq6_Kv0Rs1ujTE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN</title><source>esp@cenet</source><creator>CLEVENGER, LARRY ; WISE, MICHAEL ; NARAYAN, CHANDRASEKHAR ; HSU, LOUIS L ; STEPHENS, JEREMY K</creator><creatorcontrib>CLEVENGER, LARRY ; WISE, MICHAEL ; NARAYAN, CHANDRASEKHAR ; HSU, LOUIS L ; STEPHENS, JEREMY K</creatorcontrib><description>An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.</description><language>ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080731&amp;DB=EPODOC&amp;CC=DE&amp;NR=60132435T2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080731&amp;DB=EPODOC&amp;CC=DE&amp;NR=60132435T2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CLEVENGER, LARRY</creatorcontrib><creatorcontrib>WISE, MICHAEL</creatorcontrib><creatorcontrib>NARAYAN, CHANDRASEKHAR</creatorcontrib><creatorcontrib>HSU, LOUIS L</creatorcontrib><creatorcontrib>STEPHENS, JEREMY K</creatorcontrib><title>PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN</title><description>An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi0EKwjAQRbtxIeodBveCWnUfm18TjINMJm5LkbgSLdT7YxUP4OrBe_-Pi-YcDBvx0UMU5EzYB3iFRJV01CR08krwDKFvYAum6CsHSXygxJYsYhyk-5wQwqDjBVIbJ-BpMbq19z7PfpwU8xpauUXunk3uu_aaH_nVWOyWq3K9Kbeq6_Kv0Rs1ujTE</recordid><startdate>20080731</startdate><enddate>20080731</enddate><creator>CLEVENGER, LARRY</creator><creator>WISE, MICHAEL</creator><creator>NARAYAN, CHANDRASEKHAR</creator><creator>HSU, LOUIS L</creator><creator>STEPHENS, JEREMY K</creator><scope>EVB</scope></search><sort><creationdate>20080731</creationdate><title>PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN</title><author>CLEVENGER, LARRY ; WISE, MICHAEL ; NARAYAN, CHANDRASEKHAR ; HSU, LOUIS L ; STEPHENS, JEREMY K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE60132435TT23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CLEVENGER, LARRY</creatorcontrib><creatorcontrib>WISE, MICHAEL</creatorcontrib><creatorcontrib>NARAYAN, CHANDRASEKHAR</creatorcontrib><creatorcontrib>HSU, LOUIS L</creatorcontrib><creatorcontrib>STEPHENS, JEREMY K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CLEVENGER, LARRY</au><au>WISE, MICHAEL</au><au>NARAYAN, CHANDRASEKHAR</au><au>HSU, LOUIS L</au><au>STEPHENS, JEREMY K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN</title><date>2008-07-31</date><risdate>2008</risdate><abstract>An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language ger
recordid cdi_epo_espacenet_DE60132435TT2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title PLANARISIERTE HALBLEITERSTRUKTUR MIT EINER LEITENDEN SICHERUNG UND DESSEN HERSTELLUNGSVERFAHREN
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T06%3A22%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CLEVENGER,%20LARRY&rft.date=2008-07-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EDE60132435TT2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true