MOS-Transistor, Halbeiterspeicherbauelement mit MOS-Transistoren und Herstellungsverfahren hierfür
A vertically structured transistor and method for manufacturing the same achieves a highly integrated semiconductor device. A pillar is vertically formed on a semiconductor substrate and forms a channel region of the transistor. A gate electrode is formed in a self-alignment fashion so as to surroun...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A vertically structured transistor and method for manufacturing the same achieves a highly integrated semiconductor device. A pillar is vertically formed on a semiconductor substrate and forms a channel region of the transistor. A gate electrode is formed in a self-alignment fashion so as to surround the sides of the pillar with a gate insulating film imposed therebetween. A source region and a drain region are formed in a lower portion and an upper portion of the pillar, respectively. The area occupied by a transistor according to the present invention is remarkably reduced. |
---|