Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen
After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the diele...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CANTARELLI, DANIELE PANSANA, PIERANGELO CRISENZA, GIUSEPPE |
description | After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE3540422C2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE3540422C2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE3540422C23</originalsourceid><addsrcrecordid>eNqNjUtuwkAQRL3JIiK5Qx8AS8iQE_AReyO2aLDLdovxYHX3CMlH4gCssuNiGSMOkFWpnurzmd2PkMZ1gkBj7GkPUYP3yXIwtMIQg1BpEi8Wp1jPRoGrzvLGP3-TcptoOSAxyPgqz6lmkMKf1XIXtYVMDRioZM8Vx16r7oUCxVBT7cbYons-JK3RQVxQVrtOfy42N7AifGUfjfOK77fOMtptD-t9juF6gg6uQoCdNtvlz2qxKop1sfxH5A-r8FxZ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen</title><source>esp@cenet</source><creator>CANTARELLI, DANIELE ; PANSANA, PIERANGELO ; CRISENZA, GIUSEPPE</creator><creatorcontrib>CANTARELLI, DANIELE ; PANSANA, PIERANGELO ; CRISENZA, GIUSEPPE</creatorcontrib><description>After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.</description><edition>7</edition><language>ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010426&DB=EPODOC&CC=DE&NR=3540422C2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010426&DB=EPODOC&CC=DE&NR=3540422C2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CANTARELLI, DANIELE</creatorcontrib><creatorcontrib>PANSANA, PIERANGELO</creatorcontrib><creatorcontrib>CRISENZA, GIUSEPPE</creatorcontrib><title>Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen</title><description>After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjUtuwkAQRL3JIiK5Qx8AS8iQE_AReyO2aLDLdovxYHX3CMlH4gCssuNiGSMOkFWpnurzmd2PkMZ1gkBj7GkPUYP3yXIwtMIQg1BpEi8Wp1jPRoGrzvLGP3-TcptoOSAxyPgqz6lmkMKf1XIXtYVMDRioZM8Vx16r7oUCxVBT7cbYons-JK3RQVxQVrtOfy42N7AifGUfjfOK77fOMtptD-t9juF6gg6uQoCdNtvlz2qxKop1sfxH5A-r8FxZ</recordid><startdate>20010426</startdate><enddate>20010426</enddate><creator>CANTARELLI, DANIELE</creator><creator>PANSANA, PIERANGELO</creator><creator>CRISENZA, GIUSEPPE</creator><scope>EVB</scope></search><sort><creationdate>20010426</creationdate><title>Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen</title><author>CANTARELLI, DANIELE ; PANSANA, PIERANGELO ; CRISENZA, GIUSEPPE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE3540422C23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>2001</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CANTARELLI, DANIELE</creatorcontrib><creatorcontrib>PANSANA, PIERANGELO</creatorcontrib><creatorcontrib>CRISENZA, GIUSEPPE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CANTARELLI, DANIELE</au><au>PANSANA, PIERANGELO</au><au>CRISENZA, GIUSEPPE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen</title><date>2001-04-26</date><risdate>2001</risdate><abstract>After growth of gate oxide, deposit and separation of a first polycrystalline silicon layer, growth of dielectric oxide and removal thereof from the transistor area, and deposit of a second polycrystalline layer, a single mask makes possible first etching of the second silicon layer and of the dielectric oxide and then of the first silicon layer of the gate oxide at the sides of the cell and transistor areas.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | ger |
recordid | cdi_epo_espacenet_DE3540422C2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T12%3A23%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CANTARELLI,%20DANIELE&rft.date=2001-04-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EDE3540422C2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |