DE2807175

Two asynchronously operating computers which are each controlled by timing periods produced by its own clock are each provided with a pulse treatment circuit which in response to a break signal, interrupts the computer operation during the following timing period. A buffer memory is used in order to transfer information from the first to the second of the computers. Because of the asynchronism there is a risk that the buffer memory becomes either totally occupied or unoccupied. The risk is eliminated by means of an address and break signal generator which generates addresses to control writing and reading of the buffer memory and generates break signals which are sent to the pulse treatment circuit of the first and second computer in order to inhibit information from being sent to the buffer memory when it is full or drawn from the buffer memory when it is empty. The writing and reading addresses are generated by means of a first and a second circulating address counter stepped by the pulse treatment circuit of the first and second computer, respectively. The break signals are generated by means of a comparator connected to the two address counters. In addition the timing periods of the operating cycles have portions during which the computer components work unreliably due to their reaction times i.e., the setting of flip-flops, the ripple in counters, etc. Therefore, a reliability device compares the phases of the timing periods produced by the two computer clocks in order to allow only break signals which are generated owing to the comparison of addresses obtained in period parts during which both address counters are reliable.