DE2555963
1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain...
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| creator | SCHULZE-SCHOELLING, HERMANN, 7031 GAERTRINGEN, DE HEYDEN, HORST VON DER BLUM, ARNOLD., 7530 PFORZHEIM, DE SCHAAL, HELMUT, 7405 DETTENHAUSEN, DE RICHTER, STEPHAN, 7030 BOEBLINGEN, DE IRRO, FRITZ |
| description | 1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain external and/or internal non-program conditions are satisfied. The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set. |
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The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1982</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19821028&DB=EPODOC&CC=DE&NR=2555963C2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19821028&DB=EPODOC&CC=DE&NR=2555963C2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SCHULZE-SCHOELLING, HERMANN, 7031 GAERTRINGEN, DE</creatorcontrib><creatorcontrib>HEYDEN, HORST VON DER</creatorcontrib><creatorcontrib>BLUM, ARNOLD., 7530 PFORZHEIM, DE</creatorcontrib><creatorcontrib>SCHAAL, HELMUT, 7405 DETTENHAUSEN, DE</creatorcontrib><creatorcontrib>RICHTER, STEPHAN, 7030 BOEBLINGEN, DE</creatorcontrib><creatorcontrib>IRRO, FRITZ</creatorcontrib><title>DE2555963</title><description>1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain external and/or internal non-program conditions are satisfied. The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. 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The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | DE2555963 |
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