Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating
The chip carrier device for an encased chip arrangement has a chip carrier (11). One chip contact side (24) has a strip conductor structure with a contact surface extending to one external contact side (25) on the chip carrier and assigned to one chip (18) with through-plating. The chip carrier has...
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creator | ROHDE, HARTMUT WENDLAND, GERHILD |
description | The chip carrier device for an encased chip arrangement has a chip carrier (11). One chip contact side (24) has a strip conductor structure with a contact surface extending to one external contact side (25) on the chip carrier and assigned to one chip (18) with through-plating. The chip carrier has other through-plating connected to the strip conductor structure for connecting to test connectors on a test plate.
Chipträgeranordnung (10) für eine gehäuste Chipanordnung mit einem Chipträger (11), der auf einer Chipkontaktseite (24) eine Leiterbahnstruktur (12) mit zu einer Außenkontaktseite (25) des Chipträgers reichenden und zumindest einem Chip (18) mit jeweils einer Durchkontaktierung (14) zugeordneten Anschlußfläche (17) aufweist, wobei der Chipträger (11) weitere mit der Leiterbahnstruktur (12) verbundene Durchkontaktierungen (14) aufweist, die zur Kontaktierung mit Prüfanschlüssen (32) einer Prüfplatine (29, 30) dienen. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE19831634A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE19831634A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE19831634A13</originalsourceid><addsrcrecordid>eNqNjUFOw0AMRbNhgQp3MAfoIgpCsKxKKw7AvnIdJ2Np4hnZDoijcTumlAOw8v_S-3633fc-SQVCM2GDkT-EGKqVcaWQojAVA1RgJXQegS50g1FnXlgDPiXSL5CZwoQwQ7AHuCw1yyTs1w0VDaSAhSmhii_Qnvt69jBsAzh_AUIrV_Rib-LWW1iNm2GESFbWOW1rxhCd77qbCbPz_d_ddA_Hw_v-bcu1nNgrEivH6fXQvzwP_dPwuOuH_zA_S7Ffhg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating</title><source>esp@cenet</source><creator>ROHDE, HARTMUT ; WENDLAND, GERHILD</creator><creatorcontrib>ROHDE, HARTMUT ; WENDLAND, GERHILD</creatorcontrib><description>The chip carrier device for an encased chip arrangement has a chip carrier (11). One chip contact side (24) has a strip conductor structure with a contact surface extending to one external contact side (25) on the chip carrier and assigned to one chip (18) with through-plating. The chip carrier has other through-plating connected to the strip conductor structure for connecting to test connectors on a test plate.
Chipträgeranordnung (10) für eine gehäuste Chipanordnung mit einem Chipträger (11), der auf einer Chipkontaktseite (24) eine Leiterbahnstruktur (12) mit zu einer Außenkontaktseite (25) des Chipträgers reichenden und zumindest einem Chip (18) mit jeweils einer Durchkontaktierung (14) zugeordneten Anschlußfläche (17) aufweist, wobei der Chipträger (11) weitere mit der Leiterbahnstruktur (12) verbundene Durchkontaktierungen (14) aufweist, die zur Kontaktierung mit Prüfanschlüssen (32) einer Prüfplatine (29, 30) dienen.</description><edition>7</edition><language>eng ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000127&DB=EPODOC&CC=DE&NR=19831634A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000127&DB=EPODOC&CC=DE&NR=19831634A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROHDE, HARTMUT</creatorcontrib><creatorcontrib>WENDLAND, GERHILD</creatorcontrib><title>Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating</title><description>The chip carrier device for an encased chip arrangement has a chip carrier (11). One chip contact side (24) has a strip conductor structure with a contact surface extending to one external contact side (25) on the chip carrier and assigned to one chip (18) with through-plating. The chip carrier has other through-plating connected to the strip conductor structure for connecting to test connectors on a test plate.
Chipträgeranordnung (10) für eine gehäuste Chipanordnung mit einem Chipträger (11), der auf einer Chipkontaktseite (24) eine Leiterbahnstruktur (12) mit zu einer Außenkontaktseite (25) des Chipträgers reichenden und zumindest einem Chip (18) mit jeweils einer Durchkontaktierung (14) zugeordneten Anschlußfläche (17) aufweist, wobei der Chipträger (11) weitere mit der Leiterbahnstruktur (12) verbundene Durchkontaktierungen (14) aufweist, die zur Kontaktierung mit Prüfanschlüssen (32) einer Prüfplatine (29, 30) dienen.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjUFOw0AMRbNhgQp3MAfoIgpCsKxKKw7AvnIdJ2Np4hnZDoijcTumlAOw8v_S-3633fc-SQVCM2GDkT-EGKqVcaWQojAVA1RgJXQegS50g1FnXlgDPiXSL5CZwoQwQ7AHuCw1yyTs1w0VDaSAhSmhii_Qnvt69jBsAzh_AUIrV_Rib-LWW1iNm2GESFbWOW1rxhCd77qbCbPz_d_ddA_Hw_v-bcu1nNgrEivH6fXQvzwP_dPwuOuH_zA_S7Ffhg</recordid><startdate>20000127</startdate><enddate>20000127</enddate><creator>ROHDE, HARTMUT</creator><creator>WENDLAND, GERHILD</creator><scope>EVB</scope></search><sort><creationdate>20000127</creationdate><title>Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating</title><author>ROHDE, HARTMUT ; WENDLAND, GERHILD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE19831634A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; ger</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>ROHDE, HARTMUT</creatorcontrib><creatorcontrib>WENDLAND, GERHILD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROHDE, HARTMUT</au><au>WENDLAND, GERHILD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating</title><date>2000-01-27</date><risdate>2000</risdate><abstract>The chip carrier device for an encased chip arrangement has a chip carrier (11). One chip contact side (24) has a strip conductor structure with a contact surface extending to one external contact side (25) on the chip carrier and assigned to one chip (18) with through-plating. The chip carrier has other through-plating connected to the strip conductor structure for connecting to test connectors on a test plate.
Chipträgeranordnung (10) für eine gehäuste Chipanordnung mit einem Chipträger (11), der auf einer Chipkontaktseite (24) eine Leiterbahnstruktur (12) mit zu einer Außenkontaktseite (25) des Chipträgers reichenden und zumindest einem Chip (18) mit jeweils einer Durchkontaktierung (14) zugeordneten Anschlußfläche (17) aufweist, wobei der Chipträger (11) weitere mit der Leiterbahnstruktur (12) verbundene Durchkontaktierungen (14) aufweist, die zur Kontaktierung mit Prüfanschlüssen (32) einer Prüfplatine (29, 30) dienen.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
title | Chip carrier device production for an encased chip arrangement with an electrical test simplifies chip contact mechanism on substrates by a strip conductor structure and through-plating |
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