Digital circuit verification method, especially for verification of multiplication structure containing circuits, in which a reference circuit is first matched to the circuit to be verified to speed the verification process

Method for verifying digital circuits, whereby a digital circuit (6) that is to be verified is compared with a reference description (5) so that by use of equivalence testing errors can be detected in the digital circuit. Accordingly, from a number of different possible circuit implementations (7),...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MUELLER-BRAHMS, MARTIN, HOERETH, STEFAN, RUDLOF, THOMAS
Format:	Patent
Sprache:	eng ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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