Verfahren zum Behandeln von Designfehlern eines Layouts einer integrierten Schaltung

Verfahren zum Behandeln von Designfehlern eines Layouts einer integrierten Schaltung

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1. Verfasser: HOFSAESS, MARKUS
Format: Patent
Sprache:ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title Verfahren zum Behandeln von Designfehlern eines Layouts einer integrierten Schaltung
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