Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche

Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche

Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: GLASHAUSER, WALTER, GAIDIS, MICHAEL C, RATH, DAVID L, COSTRINI, GREG
Format: Patent
Sprache:ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator GLASHAUSER, WALTER
GAIDIS, MICHAEL C
RATH, DAVID L
COSTRINI, GREG
description Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_DE102004029355B4</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>DE102004029355B4</sourcerecordid><originalsourceid>FETCH-epo_espacenet_DE102004029355B43</originalsourceid><addsrcrecordid>eNrjZPAPSy1KS8woSs1TyM0sUShOzUkqLkksLU5PLcpMzihJLUktUvBNLM5OVagqzVUAKi7KzAPK5SmkACWiUnNyUvNyEivzS0vScg4vSc5I5WFgTUvMKU7lhdLcDKpuriHOHrqpBfnxqcUFicmpeakl8S6uhgZGBgYmBkaWxqamTibGxKoDAMfCOgg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche</title><source>esp@cenet</source><creator>GLASHAUSER, WALTER ; GAIDIS, MICHAEL C ; RATH, DAVID L ; COSTRINI, GREG</creator><creatorcontrib>GLASHAUSER, WALTER ; GAIDIS, MICHAEL C ; RATH, DAVID L ; COSTRINI, GREG</creatorcontrib><description>Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.</description><language>ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080515&amp;DB=EPODOC&amp;CC=DE&amp;NR=102004029355B4$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080515&amp;DB=EPODOC&amp;CC=DE&amp;NR=102004029355B4$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GLASHAUSER, WALTER</creatorcontrib><creatorcontrib>GAIDIS, MICHAEL C</creatorcontrib><creatorcontrib>RATH, DAVID L</creatorcontrib><creatorcontrib>COSTRINI, GREG</creatorcontrib><title>Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche</title><description>Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAPSy1KS8woSs1TyM0sUShOzUkqLkksLU5PLcpMzihJLUktUvBNLM5OVagqzVUAKi7KzAPK5SmkACWiUnNyUvNyEivzS0vScg4vSc5I5WFgTUvMKU7lhdLcDKpuriHOHrqpBfnxqcUFicmpeakl8S6uhgZGBgYmBkaWxqamTibGxKoDAMfCOgg</recordid><startdate>20080515</startdate><enddate>20080515</enddate><creator>GLASHAUSER, WALTER</creator><creator>GAIDIS, MICHAEL C</creator><creator>RATH, DAVID L</creator><creator>COSTRINI, GREG</creator><scope>EVB</scope></search><sort><creationdate>20080515</creationdate><title>Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche</title><author>GLASHAUSER, WALTER ; GAIDIS, MICHAEL C ; RATH, DAVID L ; COSTRINI, GREG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_DE102004029355B43</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ger</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GLASHAUSER, WALTER</creatorcontrib><creatorcontrib>GAIDIS, MICHAEL C</creatorcontrib><creatorcontrib>RATH, DAVID L</creatorcontrib><creatorcontrib>COSTRINI, GREG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GLASHAUSER, WALTER</au><au>GAIDIS, MICHAEL C</au><au>RATH, DAVID L</au><au>COSTRINI, GREG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche</title><date>2008-05-15</date><risdate>2008</risdate><abstract>Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language ger
recordid cdi_epo_espacenet_DE102004029355B4
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Verfahren mit selbstausgerichteter Maske zum Verringern der Zellenlayoutfläche
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T10%3A52%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GLASHAUSER,%20WALTER&rft.date=2008-05-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EDE102004029355B4%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true