Vorrichtung zum Minimieren von Adressenbits und Ladevorgängen in einem Adressenraum

Vorrichtung zum Minimieren von Adressenbits und Ladevorgängen in einem Adressenraum

An address space of a random access memory ("RAM") is overlaid over an address space of a read-only memory ("ROM") minimizing traditional address bits and loading of an address decoder. Word lines in the ROM in the overlap region are constructed without programming FETs. When the...

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Hauptverfasser: LIAO, KEVIN, BROCKMANN, RUSSELL C
Format: Patent
Sprache:ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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BROCKMANN, RUSSELL C
description An address space of a random access memory ("RAM") is overlaid over an address space of a read-only memory ("ROM") minimizing traditional address bits and loading of an address decoder. Word lines in the ROM in the overlap region are constructed without programming FETs. When the overlap region is addressed, the ROM is unable to change a pre-charged level of the ROM because of the lack of programming FETs. The RAM, however, is free to either leave the pre-charged level unchanged or to drive a node, as required. Thus, conflicts between the ROM and the RAM in the overlap region are eliminated and additional address bit are saved, and loading of address decoders is minimized.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Vorrichtung zum Minimieren von Adressenbits und Ladevorgängen in einem Adressenraum
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