Computer system

M stkov² ip (34) PCI/ISA (d le m stek) je p°ipojen mezi prvn sb rnici (30), p°ednostn PCI sb rnici, a druhou sb rnici (32), p°ednostn ISA sb rnici, v po ta ov m syst mu. PCI master (42) v syst mu aktivuje informace o adrese a adresn parit na prvn sb rnici (30) pro zah jen transakce master-slave p°es PCI sb rnici. M stek (34) obsahuje logiku (60) pro porovn v n informac o adrese a adresn parit a generov n sign lu chyby adresn parity, nastane-li chyba adresn parity. M stek (34) tak obsahuje pam ov² PCI slave (40), kter² p°ij m sign l chyby adresn parity a generuje jako odezvu sign l c lov ho zru en , po adoval-li ji pam ov² PCI slave (40) adresu aktivac sign lu v²b ru za° zen . M stek (34) tak obsahuje logiku, kter zamezuje sign lu c lov ho zru en v °en na prvn sb rnici (30), kdykoli tato logika p°ijme jak sign l o chyb adresn parity, tak sign l v²b ru za° zen . To umo uje masteru prov st zru en mastera a zabra uje PCI slavu (40) na m stku v prov d n c lov ho zru en , nastane-li chyba adresn parity.\ A peripheral controller interconnect/industry standard architecture (PCI/ISA) bridge chip (34)(hereinafter bridge) is coupled between a first bus (30), preferably the PCI bus a second bus (32), preferably ISA bus (32) in a computer system. A PCI master (42) in the system asserts address and address parity information on the PCI bus (30) to initiate a master-slave transaction over the PCI bus. The bridge (34) includes logic (60) for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge (34) also includes a PCI slave (40) that receives the address parity error signal and generates a target-abort signal in response if the PCI slave (40) has already claimed the address by asserting a device select signal. The bridge (34) also includes logic that prevents the target-abort signal from propagating to the PCI bus (30) whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave (40) on the bridge from performing a target-abort when there is an address parity error.