Semiconductor structure
A semiconductor structure includes a substrate; an isolation structure over the substrate; two source/drain structures extending from the substrate; the semiconductor channel layer is suspended above the substrate and is connected with the two source/drain structures; a high dielectric constant meta...
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creator | LIU CHANGMIAO CHENG, CHUN-FAI |
description | A semiconductor structure includes a substrate; an isolation structure over the substrate; two source/drain structures extending from the substrate; the semiconductor channel layer is suspended above the substrate and is connected with the two source/drain structures; a high dielectric constant metal gate stack located between the two source/drain structures and surrounding each of the semiconductor channel layers; gate spacers located on both sidewalls of the high dielectric constant metal gate stack; a dielectric internal spacer vertically disposed between two adjacent layers of the semiconductor channel layer and vertically located between the gate spacer and the topmost layer of the semiconductor channel layer; and a sidewall spacer over the isolation structure and contacting sidewalls of the two source/drain structures, where the sidewall spacer extends over a bottom surface of a topmost layer of the semiconductor channel layer.
一种半导体结构,包含基底;隔离结构,位于基底上方;两源极/漏极结构,从基底延伸;半导体通道层,悬置于基底上方并连接两源极/漏极结构;高介电常数金属栅极堆 |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN221304690UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN221304690UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN221304690UU3</originalsourceid><addsrcrecordid>eNrjZBAPTs3NTM7PSylNLskvUiguKQIySotSeRhY0xJzilN5oTQ3g5Kba4izh25qQX58anFBYnJqXmpJvLOfkZGhsYGJmaVBaKgxUYoASi8jOA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor structure</title><source>esp@cenet</source><creator>LIU CHANGMIAO ; CHENG, CHUN-FAI</creator><creatorcontrib>LIU CHANGMIAO ; CHENG, CHUN-FAI</creatorcontrib><description>A semiconductor structure includes a substrate; an isolation structure over the substrate; two source/drain structures extending from the substrate; the semiconductor channel layer is suspended above the substrate and is connected with the two source/drain structures; a high dielectric constant metal gate stack located between the two source/drain structures and surrounding each of the semiconductor channel layers; gate spacers located on both sidewalls of the high dielectric constant metal gate stack; a dielectric internal spacer vertically disposed between two adjacent layers of the semiconductor channel layer and vertically located between the gate spacer and the topmost layer of the semiconductor channel layer; and a sidewall spacer over the isolation structure and contacting sidewalls of the two source/drain structures, where the sidewall spacer extends over a bottom surface of a topmost layer of the semiconductor channel layer.
一种半导体结构,包含基底;隔离结构,位于基底上方;两源极/漏极结构,从基底延伸;半导体通道层,悬置于基底上方并连接两源极/漏极结构;高介电常数金属栅极堆</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240709&DB=EPODOC&CC=CN&NR=221304690U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,782,887,25573,76557</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240709&DB=EPODOC&CC=CN&NR=221304690U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIU CHANGMIAO</creatorcontrib><creatorcontrib>CHENG, CHUN-FAI</creatorcontrib><title>Semiconductor structure</title><description>A semiconductor structure includes a substrate; an isolation structure over the substrate; two source/drain structures extending from the substrate; the semiconductor channel layer is suspended above the substrate and is connected with the two source/drain structures; a high dielectric constant metal gate stack located between the two source/drain structures and surrounding each of the semiconductor channel layers; gate spacers located on both sidewalls of the high dielectric constant metal gate stack; a dielectric internal spacer vertically disposed between two adjacent layers of the semiconductor channel layer and vertically located between the gate spacer and the topmost layer of the semiconductor channel layer; and a sidewall spacer over the isolation structure and contacting sidewalls of the two source/drain structures, where the sidewall spacer extends over a bottom surface of a topmost layer of the semiconductor channel layer.
一种半导体结构,包含基底;隔离结构,位于基底上方;两源极/漏极结构,从基底延伸;半导体通道层,悬置于基底上方并连接两源极/漏极结构;高介电常数金属栅极堆</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAPTs3NTM7PSylNLskvUiguKQIySotSeRhY0xJzilN5oTQ3g5Kba4izh25qQX58anFBYnJqXmpJvLOfkZGhsYGJmaVBaKgxUYoASi8jOA</recordid><startdate>20240709</startdate><enddate>20240709</enddate><creator>LIU CHANGMIAO</creator><creator>CHENG, CHUN-FAI</creator><scope>EVB</scope></search><sort><creationdate>20240709</creationdate><title>Semiconductor structure</title><author>LIU CHANGMIAO ; CHENG, CHUN-FAI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN221304690UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIU CHANGMIAO</creatorcontrib><creatorcontrib>CHENG, CHUN-FAI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIU CHANGMIAO</au><au>CHENG, CHUN-FAI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor structure</title><date>2024-07-09</date><risdate>2024</risdate><abstract>A semiconductor structure includes a substrate; an isolation structure over the substrate; two source/drain structures extending from the substrate; the semiconductor channel layer is suspended above the substrate and is connected with the two source/drain structures; a high dielectric constant metal gate stack located between the two source/drain structures and surrounding each of the semiconductor channel layers; gate spacers located on both sidewalls of the high dielectric constant metal gate stack; a dielectric internal spacer vertically disposed between two adjacent layers of the semiconductor channel layer and vertically located between the gate spacer and the topmost layer of the semiconductor channel layer; and a sidewall spacer over the isolation structure and contacting sidewalls of the two source/drain structures, where the sidewall spacer extends over a bottom surface of a topmost layer of the semiconductor channel layer.
一种半导体结构,包含基底;隔离结构,位于基底上方;两源极/漏极结构,从基底延伸;半导体通道层,悬置于基底上方并连接两源极/漏极结构;高介电常数金属栅极堆</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor structure |
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