Bonding interconnection structure and multi-chip assembly
The utility model relates to the field of hybrid integrated circuit assembly, and discloses a bonding interconnection structure and a multi-chip assembly. The chip is arranged on the circuit substrate; the solder ball is arranged on a chip bonding pad of the chip, and the surface, far away from the...
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creator | REN SHUANGSHUANG CHEN JIE LIN LI LIU YONGZHI LI YE KIM DAE-LIM DAI HAIFENG |
description | The utility model relates to the field of hybrid integrated circuit assembly, and discloses a bonding interconnection structure and a multi-chip assembly. The chip is arranged on the circuit substrate; the solder ball is arranged on a chip bonding pad of the chip, and the surface, far away from the chip bonding pad, of the solder ball is a platform surface; and two ends of the bonding lead are respectively bonded with the platform surface of the solder ball and the circuit substrate. According to the bonding interconnection structure, the welding balls with the platform surfaces are arranged on the chip bonding pads of the chips, the bonding wires are bonded with the platform surfaces of the welding balls and the circuit substrate, namely, the bonding wires are bonded in a ball bonding mode, the ball bonding speed is high, and the bonding interconnection structure is suitable for large-scale production; the requirement of ball bonding on an interface is relatively low, and the compatibility is high; moreover, |
format | Patent |
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According to the bonding interconnection structure, the welding balls with the platform surfaces are arranged on the chip bonding pads of the chips, the bonding wires are bonded with the platform surfaces of the welding balls and the circuit substrate, namely, the bonding wires are bonded in a ball bonding mode, the ball bonding speed is high, and the bonding interconnection structure is suitable for large-scale production; the requirement of ball bonding on an interface is relatively low, and the compatibility is high; moreover,</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0ys9LycxLV8jMK0ktSs7Py0tNLsnMz1MoLikqTS4pLUpVSMxLUcgtzSnJ1E3OyCxQSCwuTs1NyqnkYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxzn5GhhYmlhYGZiahocZEKQIA99IwOw</recordid><startdate>20230217</startdate><enddate>20230217</enddate><creator>REN SHUANGSHUANG</creator><creator>CHEN JIE</creator><creator>LIN LI</creator><creator>LIU YONGZHI</creator><creator>LI YE</creator><creator>KIM DAE-LIM</creator><creator>DAI HAIFENG</creator><scope>EVB</scope></search><sort><creationdate>20230217</creationdate><title>Bonding interconnection structure and multi-chip assembly</title><author>REN SHUANGSHUANG ; CHEN JIE ; LIN LI ; LIU YONGZHI ; LI YE ; KIM DAE-LIM ; DAI HAIFENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN218498064UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>REN SHUANGSHUANG</creatorcontrib><creatorcontrib>CHEN JIE</creatorcontrib><creatorcontrib>LIN LI</creatorcontrib><creatorcontrib>LIU YONGZHI</creatorcontrib><creatorcontrib>LI YE</creatorcontrib><creatorcontrib>KIM DAE-LIM</creatorcontrib><creatorcontrib>DAI HAIFENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>REN SHUANGSHUANG</au><au>CHEN JIE</au><au>LIN LI</au><au>LIU YONGZHI</au><au>LI YE</au><au>KIM DAE-LIM</au><au>DAI HAIFENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Bonding interconnection structure and multi-chip assembly</title><date>2023-02-17</date><risdate>2023</risdate><abstract>The utility model relates to the field of hybrid integrated circuit assembly, and discloses a bonding interconnection structure and a multi-chip assembly. The chip is arranged on the circuit substrate; the solder ball is arranged on a chip bonding pad of the chip, and the surface, far away from the chip bonding pad, of the solder ball is a platform surface; and two ends of the bonding lead are respectively bonded with the platform surface of the solder ball and the circuit substrate. According to the bonding interconnection structure, the welding balls with the platform surfaces are arranged on the chip bonding pads of the chips, the bonding wires are bonded with the platform surfaces of the welding balls and the circuit substrate, namely, the bonding wires are bonded in a ball bonding mode, the ball bonding speed is high, and the bonding interconnection structure is suitable for large-scale production; the requirement of ball bonding on an interface is relatively low, and the compatibility is high; moreover,</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Bonding interconnection structure and multi-chip assembly |
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