Chip packaging structure

Chip packaging structure

The utility model provides a chip packaging structure. The structure comprises a chip substrate, a first metal layer, an insulating layer and a second metal layer. The chip base body comprises a base material with a first surface and a second surface which are oppositely arranged, and the first surf...

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1. Verfasser: HONG FANGYUAN
Format: Patent
Sprache:chi ; eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description The utility model provides a chip packaging structure. The structure comprises a chip substrate, a first metal layer, an insulating layer and a second metal layer. The chip base body comprises a base material with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a chip main body; the first metal layer is arranged on the second surface of the chip substrate, and the first metal layer is provided with a heat dissipation main body; the insulating layer is arranged on one side, far away from the base material, of the first metal layer; the second metal layer is arranged on the side, away from the base material, of the insulating layer, the second metal layer comprises an electric connection part and a heat dissipation part, the heat dissipation part is in heat conduction connection with the heat dissipation main body, and the electric connection part is electrically connected with the chip main body. Therefore, heat generated by the chip main body is dissi
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN217387135UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN217387135UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN217387135UU3</originalsourceid><addsrcrecordid>eNrjZJBwzsgsUChITM5OTM_MS1coLikqTS4pLUrlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxUAdqXmpJfHOfkaG5sYW5obGpqGhxkQpAgBF6yM3</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip packaging structure</title><source>esp@cenet</source><creator>HONG FANGYUAN</creator><creatorcontrib>HONG FANGYUAN</creatorcontrib><description>The utility model provides a chip packaging structure. The structure comprises a chip substrate, a first metal layer, an insulating layer and a second metal layer. The chip base body comprises a base material with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a chip main body; the first metal layer is arranged on the second surface of the chip substrate, and the first metal layer is provided with a heat dissipation main body; the insulating layer is arranged on one side, far away from the base material, of the first metal layer; the second metal layer is arranged on the side, away from the base material, of the insulating layer, the second metal layer comprises an electric connection part and a heat dissipation part, the heat dissipation part is in heat conduction connection with the heat dissipation main body, and the electric connection part is electrically connected with the chip main body. Therefore, heat generated by the chip main body is dissi</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220906&amp;DB=EPODOC&amp;CC=CN&amp;NR=217387135U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220906&amp;DB=EPODOC&amp;CC=CN&amp;NR=217387135U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HONG FANGYUAN</creatorcontrib><title>Chip packaging structure</title><description>The utility model provides a chip packaging structure. The structure comprises a chip substrate, a first metal layer, an insulating layer and a second metal layer. The chip base body comprises a base material with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a chip main body; the first metal layer is arranged on the second surface of the chip substrate, and the first metal layer is provided with a heat dissipation main body; the insulating layer is arranged on one side, far away from the base material, of the first metal layer; the second metal layer is arranged on the side, away from the base material, of the insulating layer, the second metal layer comprises an electric connection part and a heat dissipation part, the heat dissipation part is in heat conduction connection with the heat dissipation main body, and the electric connection part is electrically connected with the chip main body. Therefore, heat generated by the chip main body is dissi</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBwzsgsUChITM5OTM_MS1coLikqTS4pLUrlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxUAdqXmpJfHOfkaG5sYW5obGpqGhxkQpAgBF6yM3</recordid><startdate>20220906</startdate><enddate>20220906</enddate><creator>HONG FANGYUAN</creator><scope>EVB</scope></search><sort><creationdate>20220906</creationdate><title>Chip packaging structure</title><author>HONG FANGYUAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN217387135UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HONG FANGYUAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HONG FANGYUAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip packaging structure</title><date>2022-09-06</date><risdate>2022</risdate><abstract>The utility model provides a chip packaging structure. The structure comprises a chip substrate, a first metal layer, an insulating layer and a second metal layer. The chip base body comprises a base material with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a chip main body; the first metal layer is arranged on the second surface of the chip substrate, and the first metal layer is provided with a heat dissipation main body; the insulating layer is arranged on one side, far away from the base material, of the first metal layer; the second metal layer is arranged on the side, away from the base material, of the insulating layer, the second metal layer comprises an electric connection part and a heat dissipation part, the heat dissipation part is in heat conduction connection with the heat dissipation main body, and the electric connection part is electrically connected with the chip main body. Therefore, heat generated by the chip main body is dissi</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip packaging structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T12%3A09%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HONG%20FANGYUAN&rft.date=2022-09-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN217387135UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true