Packaging structure of semiconductor device

The utility model provides a packaging structure of a semiconductor device. The packaging structure comprises a substrate, wherein a welding area is arranged on the upper surface of the substrate; a first semiconductor device; a conductive bump disposed on the pad of the lower surface of the first s...

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Hauptverfasser: YANG QINGHUA, GAO ZHENHAO
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creator YANG QINGHUA
GAO ZHENHAO
description The utility model provides a packaging structure of a semiconductor device. The packaging structure comprises a substrate, wherein a welding area is arranged on the upper surface of the substrate; a first semiconductor device; a conductive bump disposed on the pad of the lower surface of the first semiconductor device for electrically connecting to the pad in the solder region; a second semiconductor device disposed over the first semiconductor device; a conductive lead disposed on the pad on the upper surface of the second semiconductor device for electrically connecting to the pad in the solder region; and an encapsulant covering the first semiconductor device, the conductive bump, the second semiconductor device and the conductive lead. According to the packaging structure of the semiconductor device, the size of the packaging structure of the semiconductor device can be reduced, the utilization rate of the packaging substrate is improved, and the cost of the packaging structure of the semiconductor device
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN217182167UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN217182167UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN217182167UU3</originalsourceid><addsrcrecordid>eNrjZNAOSEzOTkzPzEtXKC4pKk0uKS1KVchPUyhOzc1Mzs9LAYrkFymkpJZlJqfyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz8jQ3NDCyNDM_PQUGOiFAEA55Mqpg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packaging structure of semiconductor device</title><source>esp@cenet</source><creator>YANG QINGHUA ; GAO ZHENHAO</creator><creatorcontrib>YANG QINGHUA ; GAO ZHENHAO</creatorcontrib><description>The utility model provides a packaging structure of a semiconductor device. The packaging structure comprises a substrate, wherein a welding area is arranged on the upper surface of the substrate; a first semiconductor device; a conductive bump disposed on the pad of the lower surface of the first semiconductor device for electrically connecting to the pad in the solder region; a second semiconductor device disposed over the first semiconductor device; a conductive lead disposed on the pad on the upper surface of the second semiconductor device for electrically connecting to the pad in the solder region; and an encapsulant covering the first semiconductor device, the conductive bump, the second semiconductor device and the conductive lead. According to the packaging structure of the semiconductor device, the size of the packaging structure of the semiconductor device can be reduced, the utilization rate of the packaging substrate is improved, and the cost of the packaging structure of the semiconductor device</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220812&amp;DB=EPODOC&amp;CC=CN&amp;NR=217182167U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220812&amp;DB=EPODOC&amp;CC=CN&amp;NR=217182167U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANG QINGHUA</creatorcontrib><creatorcontrib>GAO ZHENHAO</creatorcontrib><title>Packaging structure of semiconductor device</title><description>The utility model provides a packaging structure of a semiconductor device. The packaging structure comprises a substrate, wherein a welding area is arranged on the upper surface of the substrate; a first semiconductor device; a conductive bump disposed on the pad of the lower surface of the first semiconductor device for electrically connecting to the pad in the solder region; a second semiconductor device disposed over the first semiconductor device; a conductive lead disposed on the pad on the upper surface of the second semiconductor device for electrically connecting to the pad in the solder region; and an encapsulant covering the first semiconductor device, the conductive bump, the second semiconductor device and the conductive lead. According to the packaging structure of the semiconductor device, the size of the packaging structure of the semiconductor device can be reduced, the utilization rate of the packaging substrate is improved, and the cost of the packaging structure of the semiconductor device</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAOSEzOTkzPzEtXKC4pKk0uKS1KVchPUyhOzc1Mzs9LAYrkFymkpJZlJqfyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz8jQ3NDCyNDM_PQUGOiFAEA55Mqpg</recordid><startdate>20220812</startdate><enddate>20220812</enddate><creator>YANG QINGHUA</creator><creator>GAO ZHENHAO</creator><scope>EVB</scope></search><sort><creationdate>20220812</creationdate><title>Packaging structure of semiconductor device</title><author>YANG QINGHUA ; GAO ZHENHAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN217182167UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YANG QINGHUA</creatorcontrib><creatorcontrib>GAO ZHENHAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANG QINGHUA</au><au>GAO ZHENHAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packaging structure of semiconductor device</title><date>2022-08-12</date><risdate>2022</risdate><abstract>The utility model provides a packaging structure of a semiconductor device. The packaging structure comprises a substrate, wherein a welding area is arranged on the upper surface of the substrate; a first semiconductor device; a conductive bump disposed on the pad of the lower surface of the first semiconductor device for electrically connecting to the pad in the solder region; a second semiconductor device disposed over the first semiconductor device; a conductive lead disposed on the pad on the upper surface of the second semiconductor device for electrically connecting to the pad in the solder region; and an encapsulant covering the first semiconductor device, the conductive bump, the second semiconductor device and the conductive lead. According to the packaging structure of the semiconductor device, the size of the packaging structure of the semiconductor device can be reduced, the utilization rate of the packaging substrate is improved, and the cost of the packaging structure of the semiconductor device</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Packaging structure of semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T19%3A39%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YANG%20QINGHUA&rft.date=2022-08-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN217182167UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true