Anti-warping printed circuit board

The utility model provides an anti-warping printed circuit board. The anti-warping printed circuit board comprises a plurality of working boards, the plurality of working boards comprise a plurality of working board surface layers which are symmetrical pairwise, each working board comprises a proces...

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Hauptverfasser: XU XIANSHANG, HUANG YAFEI, ZHANG GUIWU, GU MANMAN, XIANG ZHIJUN, LIU HUI
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creator XU XIANSHANG
HUANG YAFEI
ZHANG GUIWU
GU MANMAN
XIANG ZHIJUN
LIU HUI
description The utility model provides an anti-warping printed circuit board. The anti-warping printed circuit board comprises a plurality of working boards, the plurality of working boards comprise a plurality of working board surface layers which are symmetrical pairwise, each working board comprises a process frame and a plurality of board groups, each board group comprises a board group frame and at least two unit boards, and at least one process frame is provided with a frame optimization structure. Or at least one plate group frame is provided with a frame optimization structure, or at least one process frame and at least one plate group frame are provided with frame optimization structures, so that the residual copper rate difference value between every two symmetrical working plate surface layers is smaller than or equal to 10%. According to the utility model, based on the characteristics of the printed circuit board and the characteristics influencing the bending, the internal stress of the board is eliminated t
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN215956715UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN215956715UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN215956715UU3</originalsourceid><addsrcrecordid>eNrjZFByzCvJ1C1PLCrIzEtXKCjKzCtJTVFIzixKLs0sUUjKTyxK4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8c5-RoamlqZm5oamoaHGRCkCAAitJvE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Anti-warping printed circuit board</title><source>esp@cenet</source><creator>XU XIANSHANG ; HUANG YAFEI ; ZHANG GUIWU ; GU MANMAN ; XIANG ZHIJUN ; LIU HUI</creator><creatorcontrib>XU XIANSHANG ; HUANG YAFEI ; ZHANG GUIWU ; GU MANMAN ; XIANG ZHIJUN ; LIU HUI</creatorcontrib><description>The utility model provides an anti-warping printed circuit board. The anti-warping printed circuit board comprises a plurality of working boards, the plurality of working boards comprise a plurality of working board surface layers which are symmetrical pairwise, each working board comprises a process frame and a plurality of board groups, each board group comprises a board group frame and at least two unit boards, and at least one process frame is provided with a frame optimization structure. Or at least one plate group frame is provided with a frame optimization structure, or at least one process frame and at least one plate group frame are provided with frame optimization structures, so that the residual copper rate difference value between every two symmetrical working plate surface layers is smaller than or equal to 10%. According to the utility model, based on the characteristics of the printed circuit board and the characteristics influencing the bending, the internal stress of the board is eliminated t</description><language>chi ; eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220304&amp;DB=EPODOC&amp;CC=CN&amp;NR=215956715U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220304&amp;DB=EPODOC&amp;CC=CN&amp;NR=215956715U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>XU XIANSHANG</creatorcontrib><creatorcontrib>HUANG YAFEI</creatorcontrib><creatorcontrib>ZHANG GUIWU</creatorcontrib><creatorcontrib>GU MANMAN</creatorcontrib><creatorcontrib>XIANG ZHIJUN</creatorcontrib><creatorcontrib>LIU HUI</creatorcontrib><title>Anti-warping printed circuit board</title><description>The utility model provides an anti-warping printed circuit board. The anti-warping printed circuit board comprises a plurality of working boards, the plurality of working boards comprise a plurality of working board surface layers which are symmetrical pairwise, each working board comprises a process frame and a plurality of board groups, each board group comprises a board group frame and at least two unit boards, and at least one process frame is provided with a frame optimization structure. Or at least one plate group frame is provided with a frame optimization structure, or at least one process frame and at least one plate group frame are provided with frame optimization structures, so that the residual copper rate difference value between every two symmetrical working plate surface layers is smaller than or equal to 10%. According to the utility model, based on the characteristics of the printed circuit board and the characteristics influencing the bending, the internal stress of the board is eliminated t</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFByzCvJ1C1PLCrIzEtXKCjKzCtJTVFIzixKLs0sUUjKTyxK4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8c5-RoamlqZm5oamoaHGRCkCAAitJvE</recordid><startdate>20220304</startdate><enddate>20220304</enddate><creator>XU XIANSHANG</creator><creator>HUANG YAFEI</creator><creator>ZHANG GUIWU</creator><creator>GU MANMAN</creator><creator>XIANG ZHIJUN</creator><creator>LIU HUI</creator><scope>EVB</scope></search><sort><creationdate>20220304</creationdate><title>Anti-warping printed circuit board</title><author>XU XIANSHANG ; HUANG YAFEI ; ZHANG GUIWU ; GU MANMAN ; XIANG ZHIJUN ; LIU HUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN215956715UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>XU XIANSHANG</creatorcontrib><creatorcontrib>HUANG YAFEI</creatorcontrib><creatorcontrib>ZHANG GUIWU</creatorcontrib><creatorcontrib>GU MANMAN</creatorcontrib><creatorcontrib>XIANG ZHIJUN</creatorcontrib><creatorcontrib>LIU HUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>XU XIANSHANG</au><au>HUANG YAFEI</au><au>ZHANG GUIWU</au><au>GU MANMAN</au><au>XIANG ZHIJUN</au><au>LIU HUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Anti-warping printed circuit board</title><date>2022-03-04</date><risdate>2022</risdate><abstract>The utility model provides an anti-warping printed circuit board. The anti-warping printed circuit board comprises a plurality of working boards, the plurality of working boards comprise a plurality of working board surface layers which are symmetrical pairwise, each working board comprises a process frame and a plurality of board groups, each board group comprises a board group frame and at least two unit boards, and at least one process frame is provided with a frame optimization structure. Or at least one plate group frame is provided with a frame optimization structure, or at least one process frame and at least one plate group frame are provided with frame optimization structures, so that the residual copper rate difference value between every two symmetrical working plate surface layers is smaller than or equal to 10%. According to the utility model, based on the characteristics of the printed circuit board and the characteristics influencing the bending, the internal stress of the board is eliminated t</abstract><oa>free_for_read</oa></addata></record>
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subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title Anti-warping printed circuit board
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T02%3A39%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=XU%20XIANSHANG&rft.date=2022-03-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN215956715UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true