Package substrate and contain this package substrate's integrated circuit package body
The utility model relates to a package substrate and contain this package substrate's integrated circuit package body. According to the utility model discloses a package substrate of embodiment, thispackage substrate include first coincide circuit structure, second coincide circuit structure an...
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| creator | OU XIANXUN LUO GUANGLIN XU ZHIQIAN HAN JIANHUA CHENG XIAOLING |
| description | The utility model relates to a package substrate and contain this package substrate's integrated circuit package body. According to the utility model discloses a package substrate of embodiment, thispackage substrate include first coincide circuit structure, second coincide circuit structure and first dielectric layer. Wherein, this first coincide circuit structure include the first line layer, the second line layer and be located this the first line layer and this the second line layer between the capacitor medium layer. This capacitor medium layer including only with the third surface on the second surface on the first line layer and the second line layer in a direct contact's at least one first region to and bury the at least second area of electric capacity simultaneously in the direct contact constitution with the third surface on the second surface on the first line layer and the second line layer. The utility model provides a package substrate has the formula of imbedding resistance concurrently, imbed |
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According to the utility model discloses a package substrate of embodiment, thispackage substrate include first coincide circuit structure, second coincide circuit structure and first dielectric layer. Wherein, this first coincide circuit structure include the first line layer, the second line layer and be located this the first line layer and this the second line layer between the capacitor medium layer. This capacitor medium layer including only with the third surface on the second surface on the first line layer and the second line layer in a direct contact's at least one first region to and bury the at least second area of electric capacity simultaneously in the direct contact constitution with the third surface on the second surface on the first line layer and the second line layer. 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According to the utility model discloses a package substrate of embodiment, thispackage substrate include first coincide circuit structure, second coincide circuit structure and first dielectric layer. Wherein, this first coincide circuit structure include the first line layer, the second line layer and be located this the first line layer and this the second line layer between the capacitor medium layer. This capacitor medium layer including only with the third surface on the second surface on the first line layer and the second line layer in a direct contact's at least one first region to and bury the at least second area of electric capacity simultaneously in the direct contact constitution with the third surface on the second surface on the first line layer and the second line layer. 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According to the utility model discloses a package substrate of embodiment, thispackage substrate include first coincide circuit structure, second coincide circuit structure and first dielectric layer. Wherein, this first coincide circuit structure include the first line layer, the second line layer and be located this the first line layer and this the second line layer between the capacitor medium layer. This capacitor medium layer including only with the third surface on the second surface on the first line layer and the second line layer in a direct contact's at least one first region to and bury the at least second area of electric capacity simultaneously in the direct contact constitution with the third surface on the second surface on the first line layer and the second line layer. The utility model provides a package substrate has the formula of imbedding resistance concurrently, imbed</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Package substrate and contain this package substrate's integrated circuit package body |
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