Power on reset circuit suitable for low mains voltage territory

The utility model discloses a power on reset circuit suitable for low mains voltage territory. The power on reset circuit includes power supply voltage detection circuit, schmidt trigger and time delay shaping circuit, and wherein, power supply voltage detection circuit comprises resistance, electri...

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Hauptverfasser:	ZHU YONGCHENG, KUANG LIXUE, SUN ZHILIANG, HUO JUNJIE, DOU YUJIAO
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	ZHU YONGCHENG KUANG LIXUE SUN ZHILIANG HUO JUNJIE DOU YUJIAO
description	The utility model discloses a power on reset circuit suitable for low mains voltage territory. The power on reset circuit includes power supply voltage detection circuit, schmidt trigger and time delay shaping circuit, and wherein, power supply voltage detection circuit comprises resistance, electric capacity and NMOS transistor, a resistance termination power voltage VDD, and the drain terminal of another termination of resistance NMOS transistor, the bars termination power voltage VDD of NMOS transistor, its drain terminal meets schmidt trigger, its source termination ground, the drain terminal of an electric capacity termination NMOS transistor, electric capacity other end ground connection, the drain terminal of schmidt trigger's input termination NMOS transistor, its input of exporting termination time delay shaping circuit, time delay shaping circuit output power on reset signal. The power on reset circuit has realized in low mains voltage territory that the NMOS plumber does in the saturation region, c
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The power on reset circuit includes power supply voltage detection circuit, schmidt trigger and time delay shaping circuit, and wherein, power supply voltage detection circuit comprises resistance, electric capacity and NMOS transistor, a resistance termination power voltage VDD, and the drain terminal of another termination of resistance NMOS transistor, the bars termination power voltage VDD of NMOS transistor, its drain terminal meets schmidt trigger, its source termination ground, the drain terminal of an electric capacity termination NMOS transistor, electric capacity other end ground connection, the drain terminal of schmidt trigger's input termination NMOS transistor, its input of exporting termination time delay shaping circuit, time delay shaping circuit output power on reset signal. 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The power on reset circuit includes power supply voltage detection circuit, schmidt trigger and time delay shaping circuit, and wherein, power supply voltage detection circuit comprises resistance, electric capacity and NMOS transistor, a resistance termination power voltage VDD, and the drain terminal of another termination of resistance NMOS transistor, the bars termination power voltage VDD of NMOS transistor, its drain terminal meets schmidt trigger, its source termination ground, the drain terminal of an electric capacity termination NMOS transistor, electric capacity other end ground connection, the drain terminal of schmidt trigger's input termination NMOS transistor, its input of exporting termination time delay shaping circuit, time delay shaping circuit output power on reset signal. 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The power on reset circuit includes power supply voltage detection circuit, schmidt trigger and time delay shaping circuit, and wherein, power supply voltage detection circuit comprises resistance, electric capacity and NMOS transistor, a resistance termination power voltage VDD, and the drain terminal of another termination of resistance NMOS transistor, the bars termination power voltage VDD of NMOS transistor, its drain terminal meets schmidt trigger, its source termination ground, the drain terminal of an electric capacity termination NMOS transistor, electric capacity other end ground connection, the drain terminal of schmidt trigger's input termination NMOS transistor, its input of exporting termination time delay shaping circuit, time delay shaping circuit output power on reset signal. The power on reset circuit has realized in low mains voltage territory that the NMOS plumber does in the saturation region, c</abstract><oa>free_for_read</oa></addata></record>
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language	chi ; eng
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Power on reset circuit suitable for low mains voltage territory
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