Peripheral circuit of superregeneration reception series chip
The utility model discloses a peripheral circuit of superregeneration reception series chip, the VDD port of superregeneration reception series chip connects ground connection behind the electric capacity cvdd, the IN port parallel inductor lin and the electric capacity cin of superregeneration rece...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WANG ZHINIAN |
| description | The utility model discloses a peripheral circuit of superregeneration reception series chip, the VDD port of superregeneration reception series chip connects ground connection behind the electric capacity cvdd, the IN port parallel inductor lin and the electric capacity cin of superregeneration reception series chip connect after inductance losc and electric capacity cosc are parallelly connected between the DSC1 port and DSC2 port of superregeneration reception series chip, the GND port ground connection of superregeneration reception series chip, be connected with electric capacity C1 between superregeneration reception series chip FILTI port and the FILT2 port, the FILTI port with electric capacity C2 ground connection is passed through to the one end that C1 connects, and above -mentioned circuit effectively reduces the big problem of product sensitivity discreteness, increases sensitivity adjustment's convenience, has reduced the processing cost, makes the product more have the competitive advantage.
本实用 |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN206117646UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN206117646UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN206117646UU3</originalsourceid><addsrcrecordid>eNrjZLANSC3KLMhILUrMUUjOLEouzSxRyE9TKC4tSC0qSk1PzQPKlGTm5ykUpSanFoBZxUAdqcUKyRmZBTwMrGmJOcWpvFCam0HJzTXE2UM3tSA_PrW4IDEZaEBJvLOfkYGZoaG5mYlZaKgxUYoA310xuA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Peripheral circuit of superregeneration reception series chip</title><source>esp@cenet</source><creator>WANG ZHINIAN</creator><creatorcontrib>WANG ZHINIAN</creatorcontrib><description>The utility model discloses a peripheral circuit of superregeneration reception series chip, the VDD port of superregeneration reception series chip connects ground connection behind the electric capacity cvdd, the IN port parallel inductor lin and the electric capacity cin of superregeneration reception series chip connect after inductance losc and electric capacity cosc are parallelly connected between the DSC1 port and DSC2 port of superregeneration reception series chip, the GND port ground connection of superregeneration reception series chip, be connected with electric capacity C1 between superregeneration reception series chip FILTI port and the FILT2 port, the FILTI port with electric capacity C2 ground connection is passed through to the one end that C1 connects, and above -mentioned circuit effectively reduces the big problem of product sensitivity discreteness, increases sensitivity adjustment's convenience, has reduced the processing cost, makes the product more have the competitive advantage.
本实用</description><language>chi ; eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170419&DB=EPODOC&CC=CN&NR=206117646U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170419&DB=EPODOC&CC=CN&NR=206117646U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG ZHINIAN</creatorcontrib><title>Peripheral circuit of superregeneration reception series chip</title><description>The utility model discloses a peripheral circuit of superregeneration reception series chip, the VDD port of superregeneration reception series chip connects ground connection behind the electric capacity cvdd, the IN port parallel inductor lin and the electric capacity cin of superregeneration reception series chip connect after inductance losc and electric capacity cosc are parallelly connected between the DSC1 port and DSC2 port of superregeneration reception series chip, the GND port ground connection of superregeneration reception series chip, be connected with electric capacity C1 between superregeneration reception series chip FILTI port and the FILT2 port, the FILTI port with electric capacity C2 ground connection is passed through to the one end that C1 connects, and above -mentioned circuit effectively reduces the big problem of product sensitivity discreteness, increases sensitivity adjustment's convenience, has reduced the processing cost, makes the product more have the competitive advantage.
本实用</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLANSC3KLMhILUrMUUjOLEouzSxRyE9TKC4tSC0qSk1PzQPKlGTm5ykUpSanFoBZxUAdqcUKyRmZBTwMrGmJOcWpvFCam0HJzTXE2UM3tSA_PrW4IDEZaEBJvLOfkYGZoaG5mYlZaKgxUYoA310xuA</recordid><startdate>20170419</startdate><enddate>20170419</enddate><creator>WANG ZHINIAN</creator><scope>EVB</scope></search><sort><creationdate>20170419</creationdate><title>Peripheral circuit of superregeneration reception series chip</title><author>WANG ZHINIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN206117646UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG ZHINIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG ZHINIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Peripheral circuit of superregeneration reception series chip</title><date>2017-04-19</date><risdate>2017</risdate><abstract>The utility model discloses a peripheral circuit of superregeneration reception series chip, the VDD port of superregeneration reception series chip connects ground connection behind the electric capacity cvdd, the IN port parallel inductor lin and the electric capacity cin of superregeneration reception series chip connect after inductance losc and electric capacity cosc are parallelly connected between the DSC1 port and DSC2 port of superregeneration reception series chip, the GND port ground connection of superregeneration reception series chip, be connected with electric capacity C1 between superregeneration reception series chip FILTI port and the FILT2 port, the FILTI port with electric capacity C2 ground connection is passed through to the one end that C1 connects, and above -mentioned circuit effectively reduces the big problem of product sensitivity discreteness, increases sensitivity adjustment's convenience, has reduced the processing cost, makes the product more have the competitive advantage.
本实用</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN206117646UU |
| source | esp@cenet |
| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION |
| title | Peripheral circuit of superregeneration reception series chip |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T19%3A38%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WANG%20ZHINIAN&rft.date=2017-04-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN206117646UU%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |