IO line testing arrangement of ruggedized computer

The utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer, including two blocks of test circuit boards, test cable, host computer, wherein the test circuit board includes power, crystal oscillator, FPGA, PV needle mould piece, button, LED lamp, LCD...

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Hauptverfasser: ZHANG MEI, ZHAO DEWEI, LYU MEIMEI, ZHANG BIN, DING JIN, LOU ZHIXIANG, SUN JIE, LIANG DING, XU WEI, TAO ZHENGRONG
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creator ZHANG MEI
ZHAO DEWEI
LYU MEIMEI
ZHANG BIN
DING JIN
LOU ZHIXIANG
SUN JIE
LIANG DING
XU WEI
TAO ZHENGRONG
description The utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer, including two blocks of test circuit boards, test cable, host computer, wherein the test circuit board includes power, crystal oscillator, FPGA, PV needle mould piece, button, LED lamp, LCD LCD screen. A test circuit board inserts by in the survey computer CPCI slot, and the connector that the ruggedized computer was surveyed through debugging cable and quilt to the 2nd test circuit board is continuous, and two blocks of test circuit boards send the host computer with the test result through the RS232 serial ports. The utility model discloses a test circuit board pointwise is sent a signal, and all signals are received simultaneously to the 2nd test circuit board, the utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer simple structure, be convenient for implement.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN205157687UU</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN205157687UU</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN205157687UU3</originalsourceid><addsrcrecordid>eNrjZDDy9FfIycxLVShJLS7JzEtXSCwqSsxLT81NzStRyE9TKCpNT09NyaxKTVFIzs8tKC1JLeJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfHOfkYGpoam5mYW5qGhxkQpAgAi8Cz_</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>IO line testing arrangement of ruggedized computer</title><source>esp@cenet</source><creator>ZHANG MEI ; ZHAO DEWEI ; LYU MEIMEI ; ZHANG BIN ; DING JIN ; LOU ZHIXIANG ; SUN JIE ; LIANG DING ; XU WEI ; TAO ZHENGRONG</creator><creatorcontrib>ZHANG MEI ; ZHAO DEWEI ; LYU MEIMEI ; ZHANG BIN ; DING JIN ; LOU ZHIXIANG ; SUN JIE ; LIANG DING ; XU WEI ; TAO ZHENGRONG</creatorcontrib><description>The utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer, including two blocks of test circuit boards, test cable, host computer, wherein the test circuit board includes power, crystal oscillator, FPGA, PV needle mould piece, button, LED lamp, LCD LCD screen. A test circuit board inserts by in the survey computer CPCI slot, and the connector that the ruggedized computer was surveyed through debugging cable and quilt to the 2nd test circuit board is continuous, and two blocks of test circuit boards send the host computer with the test result through the RS232 serial ports. The utility model discloses a test circuit board pointwise is sent a signal, and all signals are received simultaneously to the 2nd test circuit board, the utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer simple structure, be convenient for implement.</description><language>chi ; eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160413&amp;DB=EPODOC&amp;CC=CN&amp;NR=205157687U$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160413&amp;DB=EPODOC&amp;CC=CN&amp;NR=205157687U$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHANG MEI</creatorcontrib><creatorcontrib>ZHAO DEWEI</creatorcontrib><creatorcontrib>LYU MEIMEI</creatorcontrib><creatorcontrib>ZHANG BIN</creatorcontrib><creatorcontrib>DING JIN</creatorcontrib><creatorcontrib>LOU ZHIXIANG</creatorcontrib><creatorcontrib>SUN JIE</creatorcontrib><creatorcontrib>LIANG DING</creatorcontrib><creatorcontrib>XU WEI</creatorcontrib><creatorcontrib>TAO ZHENGRONG</creatorcontrib><title>IO line testing arrangement of ruggedized computer</title><description>The utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer, including two blocks of test circuit boards, test cable, host computer, wherein the test circuit board includes power, crystal oscillator, FPGA, PV needle mould piece, button, LED lamp, LCD LCD screen. A test circuit board inserts by in the survey computer CPCI slot, and the connector that the ruggedized computer was surveyed through debugging cable and quilt to the 2nd test circuit board is continuous, and two blocks of test circuit boards send the host computer with the test result through the RS232 serial ports. The utility model discloses a test circuit board pointwise is sent a signal, and all signals are received simultaneously to the 2nd test circuit board, the utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer simple structure, be convenient for implement.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDy9FfIycxLVShJLS7JzEtXSCwqSsxLT81NzStRyE9TKCpNT09NyaxKTVFIzs8tKC1JLeJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfHOfkYGpoam5mYW5qGhxkQpAgAi8Cz_</recordid><startdate>20160413</startdate><enddate>20160413</enddate><creator>ZHANG MEI</creator><creator>ZHAO DEWEI</creator><creator>LYU MEIMEI</creator><creator>ZHANG BIN</creator><creator>DING JIN</creator><creator>LOU ZHIXIANG</creator><creator>SUN JIE</creator><creator>LIANG DING</creator><creator>XU WEI</creator><creator>TAO ZHENGRONG</creator><scope>EVB</scope></search><sort><creationdate>20160413</creationdate><title>IO line testing arrangement of ruggedized computer</title><author>ZHANG MEI ; ZHAO DEWEI ; LYU MEIMEI ; ZHANG BIN ; DING JIN ; LOU ZHIXIANG ; SUN JIE ; LIANG DING ; XU WEI ; TAO ZHENGRONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN205157687UU3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2016</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHANG MEI</creatorcontrib><creatorcontrib>ZHAO DEWEI</creatorcontrib><creatorcontrib>LYU MEIMEI</creatorcontrib><creatorcontrib>ZHANG BIN</creatorcontrib><creatorcontrib>DING JIN</creatorcontrib><creatorcontrib>LOU ZHIXIANG</creatorcontrib><creatorcontrib>SUN JIE</creatorcontrib><creatorcontrib>LIANG DING</creatorcontrib><creatorcontrib>XU WEI</creatorcontrib><creatorcontrib>TAO ZHENGRONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHANG MEI</au><au>ZHAO DEWEI</au><au>LYU MEIMEI</au><au>ZHANG BIN</au><au>DING JIN</au><au>LOU ZHIXIANG</au><au>SUN JIE</au><au>LIANG DING</au><au>XU WEI</au><au>TAO ZHENGRONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>IO line testing arrangement of ruggedized computer</title><date>2016-04-13</date><risdate>2016</risdate><abstract>The utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer, including two blocks of test circuit boards, test cable, host computer, wherein the test circuit board includes power, crystal oscillator, FPGA, PV needle mould piece, button, LED lamp, LCD LCD screen. A test circuit board inserts by in the survey computer CPCI slot, and the connector that the ruggedized computer was surveyed through debugging cable and quilt to the 2nd test circuit board is continuous, and two blocks of test circuit boards send the host computer with the test result through the RS232 serial ports. The utility model discloses a test circuit board pointwise is sent a signal, and all signals are received simultaneously to the 2nd test circuit board, the utility model discloses a based on CPCI 3U6U framework IO line testing arrangement of ruggedized computer simple structure, be convenient for implement.</abstract><oa>free_for_read</oa></addata></record>
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language chi ; eng
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subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title IO line testing arrangement of ruggedized computer
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