Register set circuit, and apparatus and system for error detection in memory cell

Register set circuit, and apparatus and system for error detection in memory cell

The utility model provides a register circuit, and an apparatus and a system for error detection in a memory unit. The apparatus comprises at least a bit line and a register set circuit, wherein the register set circuit is configured into operation by adopting a reduced voltage protection band, prov...

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Hauptverfasser: KULKARNI JAY-DEEP P, DE VIVEK K, BOWMAN KEITH A, TSCHANZ JAMES W
Format: Patent
Sprache:chi ; eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator KULKARNI JAY-DEEP P
DE VIVEK K
BOWMAN KEITH A
TSCHANZ JAMES W
description The utility model provides a register circuit, and an apparatus and a system for error detection in a memory unit. The apparatus comprises at least a bit line and a register set circuit, wherein the register set circuit is configured into operation by adopting a reduced voltage protection band, provides compensation for an error in a signal provided by at least the one bit line during an access operation process, and is configured into the following conditions, wherein the conditions comprise that: if responding to the assess operation to produce an error, the error is detected, and if the error is detected, the assess operation is repeated so as to operate through adopting the reduced voltage protection band.
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title Register set circuit, and apparatus and system for error detection in memory cell
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