Method and integrated switching circuit for increasing the immunity to interference

Method and integrated switching circuit for increasing the immunity to interference

Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor muC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock freque...

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1. Verfasser: FEY WOLFGANG,HEINZ MICHA,TRASKOV ADRIAN,MICHEL FRANK
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator FEY WOLFGANG,HEINZ MICHA,TRASKOV ADRIAN,MICHEL FRANK
description Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor muC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6') one after the other through at least one error line (3, 4).
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method and integrated switching circuit for increasing the immunity to interference
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