Method for fabricating chalcogenide-applied memory

Method for fabricating chalcogenide-applied memory

A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. Th...

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1. Verfasser: MING-HSIANG HSUEH
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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description A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1921169A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1921169A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1921169A3</originalsourceid><addsrcrecordid>eNrjZDDyTS3JyE9RSMsvUkhLTCrKTE4sycxLV0jOSMxJzk9PzctMSdVNLCjIyUxNUchNzc0vquRhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOfoaWRoaGZpaOxoRVAAAtCCts</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for fabricating chalcogenide-applied memory</title><source>esp@cenet</source><creator>MING-HSIANG HSUEH</creator><creatorcontrib>MING-HSIANG HSUEH</creatorcontrib><description>A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070228&amp;DB=EPODOC&amp;CC=CN&amp;NR=1921169A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070228&amp;DB=EPODOC&amp;CC=CN&amp;NR=1921169A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MING-HSIANG HSUEH</creatorcontrib><title>Method for fabricating chalcogenide-applied memory</title><description>A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDyTS3JyE9RSMsvUkhLTCrKTE4sycxLV0jOSMxJzk9PzctMSdVNLCjIyUxNUchNzc0vquRhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOfoaWRoaGZpaOxoRVAAAtCCts</recordid><startdate>20070228</startdate><enddate>20070228</enddate><creator>MING-HSIANG HSUEH</creator><scope>EVB</scope></search><sort><creationdate>20070228</creationdate><title>Method for fabricating chalcogenide-applied memory</title><author>MING-HSIANG HSUEH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1921169A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MING-HSIANG HSUEH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MING-HSIANG HSUEH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for fabricating chalcogenide-applied memory</title><date>2007-02-28</date><risdate>2007</risdate><abstract>A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Method for fabricating chalcogenide-applied memory
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T06%3A41%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MING-HSIANG%20HSUEH&rft.date=2007-02-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1921169A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true