Manufacturing method of semiconductor device

Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor eleme...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO
description Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1862791A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1862791A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1862791A3</originalsourceid><addsrcrecordid>eNrjZNDxTcwrTUtMLiktysxLV8hNLcnIT1HIT1MoTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOfoYWZkbmloaOxoRVAAAgyils</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Manufacturing method of semiconductor device</title><source>esp@cenet</source><creator>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</creator><creatorcontrib>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</creatorcontrib><description>Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20061115&amp;DB=EPODOC&amp;CC=CN&amp;NR=1862791A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20061115&amp;DB=EPODOC&amp;CC=CN&amp;NR=1862791A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</creatorcontrib><title>Manufacturing method of semiconductor device</title><description>Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDxTcwrTUtMLiktysxLV8hNLcnIT1HIT1MoTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHOfoYWZkbmloaOxoRVAAAgyils</recordid><startdate>20061115</startdate><enddate>20061115</enddate><creator>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</creator><scope>EVB</scope></search><sort><creationdate>20061115</creationdate><title>Manufacturing method of semiconductor device</title><author>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1862791A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>IPPOSHI TAKASHI,HORITA KATSUYUKI,MAEGAWA SHIGETO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Manufacturing method of semiconductor device</title><date>2006-11-15</date><risdate>2006</risdate><abstract>Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant. Then, after removing the resist and depositing an isolation oxide film on the whole surface, an isolation oxide film is flattened in good thickness precision in the height specified by the thickness of a silicon nitride film by performing CMP treatment which used the silicon nitride film as the polishing stopper.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_CN1862791A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Manufacturing method of semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T00%3A40%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=IPPOSHI%20TAKASHI,HORITA%20KATSUYUKI,MAEGAWA%20SHIGETO&rft.date=2006-11-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1862791A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true