Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM
The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII i...
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creator | JIANBO CHEN DUOLEI CHEN XIONGBIN MENG |
description | The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII interface and microprocessor interface is connected to FPGA parts and CPU; FPGA parts partition, process, convert Ethernet data packet into ATM cells, as well as constitute ATM cells to Ethernet data packet in order to carry out full duplex transmission data, and static binding of physical layer IDs between SMII interface and UTOPIA interface is carried out; CPU controls and manages VDSL set chips, FPGA part multiplexing chip; power source module supplies power at different voltages, and clock generation module generates clock signal. The invention can realize ADSL and VDSL access mode to be mixed inserted into ATM DSLAM system. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1581812A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1581812A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1581812A3</originalsourceid><addsrcrecordid>eNrjZLBxLChILEosKS1WSMsvUihKTczJrMrMS1dILclILcpLLVEIcwn2UUhMTk4tLgaJZ-YpOIb46gIFHX15GFjTEnOKU3mhNDeDvJtriLOHbmpBfnxqcUFicirQhHhnP0NTC0MLQyNHY8IqALA8LY8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM</title><source>esp@cenet</source><creator>JIANBO CHEN ; DUOLEI CHEN ; XIONGBIN MENG</creator><creatorcontrib>JIANBO CHEN ; DUOLEI CHEN ; XIONGBIN MENG</creatorcontrib><description>The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII interface and microprocessor interface is connected to FPGA parts and CPU; FPGA parts partition, process, convert Ethernet data packet into ATM cells, as well as constitute ATM cells to Ethernet data packet in order to carry out full duplex transmission data, and static binding of physical layer IDs between SMII interface and UTOPIA interface is carried out; CPU controls and manages VDSL set chips, FPGA part multiplexing chip; power source module supplies power at different voltages, and clock generation module generates clock signal. The invention can realize ADSL and VDSL access mode to be mixed inserted into ATM DSLAM system.</description><edition>7</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; SELECTING ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050216&DB=EPODOC&CC=CN&NR=1581812A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050216&DB=EPODOC&CC=CN&NR=1581812A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JIANBO CHEN</creatorcontrib><creatorcontrib>DUOLEI CHEN</creatorcontrib><creatorcontrib>XIONGBIN MENG</creatorcontrib><title>Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM</title><description>The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII interface and microprocessor interface is connected to FPGA parts and CPU; FPGA parts partition, process, convert Ethernet data packet into ATM cells, as well as constitute ATM cells to Ethernet data packet in order to carry out full duplex transmission data, and static binding of physical layer IDs between SMII interface and UTOPIA interface is carried out; CPU controls and manages VDSL set chips, FPGA part multiplexing chip; power source module supplies power at different voltages, and clock generation module generates clock signal. The invention can realize ADSL and VDSL access mode to be mixed inserted into ATM DSLAM system.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>SELECTING</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBxLChILEosKS1WSMsvUihKTczJrMrMS1dILclILcpLLVEIcwn2UUhMTk4tLgaJZ-YpOIb46gIFHX15GFjTEnOKU3mhNDeDvJtriLOHbmpBfnxqcUFicirQhHhnP0NTC0MLQyNHY8IqALA8LY8</recordid><startdate>20050216</startdate><enddate>20050216</enddate><creator>JIANBO CHEN</creator><creator>DUOLEI CHEN</creator><creator>XIONGBIN MENG</creator><scope>EVB</scope></search><sort><creationdate>20050216</creationdate><title>Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM</title><author>JIANBO CHEN ; DUOLEI CHEN ; XIONGBIN MENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1581812A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>SELECTING</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>JIANBO CHEN</creatorcontrib><creatorcontrib>DUOLEI CHEN</creatorcontrib><creatorcontrib>XIONGBIN MENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JIANBO CHEN</au><au>DUOLEI CHEN</au><au>XIONGBIN MENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM</title><date>2005-02-16</date><risdate>2005</risdate><abstract>The device includes following parts and connections: multiplexing chip, VDSL set chips, FPGA parts, CPU, power source module, clock generation and driving module; multiplexing chip through UTOPIA interface and microprocessor interface is connected to FPGA parts and CPU; VDSL set chips through SMII interface and microprocessor interface is connected to FPGA parts and CPU; FPGA parts partition, process, convert Ethernet data packet into ATM cells, as well as constitute ATM cells to Ethernet data packet in order to carry out full duplex transmission data, and static binding of physical layer IDs between SMII interface and UTOPIA interface is carried out; CPU controls and manages VDSL set chips, FPGA part multiplexing chip; power source module supplies power at different voltages, and clock generation module generates clock signal. The invention can realize ADSL and VDSL access mode to be mixed inserted into ATM DSLAM system.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY SELECTING TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Apparatus for realizing ethernet VDSL accessing in ATM-DSLAM |
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