IIC bus control system and method for realizing same
The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. W...
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| creator | YANXIANG FANG SHIHANG WANG |
| description | The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. When the bus is stand-by, the clock line and data line are set in high level, and when the chip microprocessor to be used for transmitting data is used to transmit the data, it is ste in low clock line, the receiving chip microprocessor can instantly produce interruption, and the receiving chip microprocessor uses the inverse first data line to receive the readiness answer signal, and transfer it into the chip microprocessor to be used for transmitting data, and said chip microprocessor can transmit serial data on the data line. It adopts same clock source, and its time sequence is synchronous, so that it does not produce time delay problem. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1581126A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1581126A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1581126A3</originalsourceid><addsrcrecordid>eNrjZDDx9HRWSCotVkjOzyspys9RKK4sLknNVUjMS1HITS3JyE9RSMsvUihKTczJrMrMS1coTsxN5WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8c5-hqYWhoZGZo7GhFUAAEKrK3I</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>IIC bus control system and method for realizing same</title><source>esp@cenet</source><creator>YANXIANG FANG ; SHIHANG WANG</creator><creatorcontrib>YANXIANG FANG ; SHIHANG WANG</creatorcontrib><description>The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. When the bus is stand-by, the clock line and data line are set in high level, and when the chip microprocessor to be used for transmitting data is used to transmit the data, it is ste in low clock line, the receiving chip microprocessor can instantly produce interruption, and the receiving chip microprocessor uses the inverse first data line to receive the readiness answer signal, and transfer it into the chip microprocessor to be used for transmitting data, and said chip microprocessor can transmit serial data on the data line. It adopts same clock source, and its time sequence is synchronous, so that it does not produce time delay problem.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050216&DB=EPODOC&CC=CN&NR=1581126A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050216&DB=EPODOC&CC=CN&NR=1581126A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANXIANG FANG</creatorcontrib><creatorcontrib>SHIHANG WANG</creatorcontrib><title>IIC bus control system and method for realizing same</title><description>The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. When the bus is stand-by, the clock line and data line are set in high level, and when the chip microprocessor to be used for transmitting data is used to transmit the data, it is ste in low clock line, the receiving chip microprocessor can instantly produce interruption, and the receiving chip microprocessor uses the inverse first data line to receive the readiness answer signal, and transfer it into the chip microprocessor to be used for transmitting data, and said chip microprocessor can transmit serial data on the data line. It adopts same clock source, and its time sequence is synchronous, so that it does not produce time delay problem.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDx9HRWSCotVkjOzyspys9RKK4sLknNVUjMS1HITS3JyE9RSMsvUihKTczJrMrMS1coTsxN5WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcUFicmpeakl8c5-hqYWhoZGZo7GhFUAAEKrK3I</recordid><startdate>20050216</startdate><enddate>20050216</enddate><creator>YANXIANG FANG</creator><creator>SHIHANG WANG</creator><scope>EVB</scope></search><sort><creationdate>20050216</creationdate><title>IIC bus control system and method for realizing same</title><author>YANXIANG FANG ; SHIHANG WANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1581126A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YANXIANG FANG</creatorcontrib><creatorcontrib>SHIHANG WANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANXIANG FANG</au><au>SHIHANG WANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>IIC bus control system and method for realizing same</title><date>2005-02-16</date><risdate>2005</risdate><abstract>The present invention relates to a IIC bus control system and its method for implementing said system. It comprises at least two chip microprocessors and data line and clock line connected with all the chip microprocessors and same clock source circuit connected with them by means of an interface. When the bus is stand-by, the clock line and data line are set in high level, and when the chip microprocessor to be used for transmitting data is used to transmit the data, it is ste in low clock line, the receiving chip microprocessor can instantly produce interruption, and the receiving chip microprocessor uses the inverse first data line to receive the readiness answer signal, and transfer it into the chip microprocessor to be used for transmitting data, and said chip microprocessor can transmit serial data on the data line. It adopts same clock source, and its time sequence is synchronous, so that it does not produce time delay problem.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | IIC bus control system and method for realizing same |
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