Universal clock generator
This invention relates to a universal clock generator containing a high frequency clock region generating high frequency clock signals and a low frequency clock region generating low frequency clock signals including at least a delay lock-in loop used in expanding feet numbers of high frequency cloc...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | This invention relates to a universal clock generator containing a high frequency clock region generating high frequency clock signals and a low frequency clock region generating low frequency clock signals including at least a delay lock-in loop used in expanding feet numbers of high frequency clock signals of the said high frequency clock region. When feet numbers of high frequency central processor clock SDRAM clock, AGP clock and PCI clock are not enough then the delay lock-in loop in the said low frequency clock region can be connected in series with them to match up the insufficient. |
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