Method for forming metallic grid
The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; fo...
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| creator | CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK |
| description | The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process. |
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The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070704&DB=EPODOC&CC=CN&NR=1324654C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070704&DB=EPODOC&CC=CN&NR=1324654C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK</creatorcontrib><title>Method for forming metallic grid</title><description>The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDwTS3JyE9RSMsvAuHczLx0hdzUksScnMxkhfSizBQeBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhLv7GdobGRiZmri7GxMhBIA_CgkzA</recordid><startdate>20070704</startdate><enddate>20070704</enddate><creator>CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK</creator><scope>EVB</scope></search><sort><creationdate>20070704</creationdate><title>Method for forming metallic grid</title><author>CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1324654CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG SUI-UK,SUN JUN-HYOP,CHOE HYONG-POK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming metallic grid</title><date>2007-07-04</date><risdate>2007</risdate><abstract>The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method for forming metallic grid |
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