Phase lock loop with phase rotator

Phase lock loop with phase rotator

The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS
description The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1265554CC</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1265554CC</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1265554CC3</originalsourceid><addsrcrecordid>eNrjZFAKyEgsTlXIyU_OBhL5BQrlmSUZCgVgwaL8ksSS_CIeBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoZGZqamri7GxMhBIAU9QllQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Phase lock loop with phase rotator</title><source>esp@cenet</source><creator>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</creator><creatorcontrib>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</creatorcontrib><description>The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060719&amp;DB=EPODOC&amp;CC=CN&amp;NR=1265554C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060719&amp;DB=EPODOC&amp;CC=CN&amp;NR=1265554C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</creatorcontrib><title>Phase lock loop with phase rotator</title><description>The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKyEgsTlXIyU_OBhL5BQrlmSUZCgVgwaL8ksSS_CIeBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoZGZqamri7GxMhBIAU9QllQ</recordid><startdate>20060719</startdate><enddate>20060719</enddate><creator>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</creator><scope>EVB</scope></search><sort><creationdate>20060719</creationdate><title>Phase lock loop with phase rotator</title><author>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1265554CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CRANFORD HAYDEN CLAVIE JR.,GARVIN STACY JEAN,NORMAN VERNON ROBERTS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Phase lock loop with phase rotator</title><date>2006-07-19</date><risdate>2006</risdate><abstract>The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_CN1265554CC
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Phase lock loop with phase rotator
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T06%3A30%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CRANFORD%20HAYDEN%20CLAVIE%20JR.,GARVIN%20STACY%20JEAN,NORMAN%20VERNON%20ROBERTS&rft.date=2006-07-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1265554CC%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true