Method for manufacturing capacitors in DRAM
A method for making capacitor with MIM structure includes generating the first dielectric layer on substrate, forming the contact windows on the dielectric layer, generating the first metal layer covering the first dielectric layer and in contact windows, sequentially generating barrier layer, the s...
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| creator | YOULUN DU JIJIN LUO |
| description | A method for making capacitor with MIM structure includes generating the first dielectric layer on substrate, forming the contact windows on the dielectric layer, generating the first metal layer covering the first dielectric layer and in contact windows, sequentially generating barrier layer, the second dielectric layer and polysilicon layer of uncontinuous semispherical particles, etching the second dielectric layer, removing the polysilicon layer, etching the barrier layer and the first metal layer, removing the second dielectric layer, patterning the limited barrier and the first metal layer and etching them, forming the third dielectric layer covering the barrier layer, the first metal layer and the first dielectric layer, and generating the second metal layer on the third dielectriclayer. |
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ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000112&DB=EPODOC&CC=CN&NR=1241029A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000112&DB=EPODOC&CC=CN&NR=1241029A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YOULUN DU</creatorcontrib><creatorcontrib>JIJIN LUO</creatorcontrib><title>Method for manufacturing capacitors in DRAM</title><description>A method for making capacitor with MIM structure includes generating the first dielectric layer on substrate, forming the contact windows on the dielectric layer, generating the first metal layer covering the first dielectric layer and in contact windows, sequentially generating barrier layer, the second dielectric layer and polysilicon layer of uncontinuous semispherical particles, etching the second dielectric layer, removing the polysilicon layer, etching the barrier layer and the first metal layer, removing the second dielectric layer, patterning the limited barrier and the first metal layer and etching them, forming the third dielectric layer covering the barrier layer, the first metal layer and the first dielectric layer, and generating the second metal layer on the third dielectriclayer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND2TS3JyE9RSMsvUshNzCtNS0wuKS3KzEtXSE4sSEzOLMkvKlbIzFNwCXL05WFgTUvMKU7lhdLcDPJuriHOHrqpBfnxqcVA5al5qSXxzn6GRiaGBkaWjsaEVQAAnKUoFA</recordid><startdate>20000112</startdate><enddate>20000112</enddate><creator>YOULUN DU</creator><creator>JIJIN LUO</creator><scope>EVB</scope></search><sort><creationdate>20000112</creationdate><title>Method for manufacturing capacitors in DRAM</title><author>YOULUN DU ; JIJIN LUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1241029A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YOULUN DU</creatorcontrib><creatorcontrib>JIJIN LUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YOULUN DU</au><au>JIJIN LUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for manufacturing capacitors in DRAM</title><date>2000-01-12</date><risdate>2000</risdate><abstract>A method for making capacitor with MIM structure includes generating the first dielectric layer on substrate, forming the contact windows on the dielectric layer, generating the first metal layer covering the first dielectric layer and in contact windows, sequentially generating barrier layer, the second dielectric layer and polysilicon layer of uncontinuous semispherical particles, etching the second dielectric layer, removing the polysilicon layer, etching the barrier layer and the first metal layer, removing the second dielectric layer, patterning the limited barrier and the first metal layer and etching them, forming the third dielectric layer covering the barrier layer, the first metal layer and the first dielectric layer, and generating the second metal layer on the third dielectriclayer.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method for manufacturing capacitors in DRAM |
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