Method of reducing loading variation during etch processing

In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	FRANK PREIN, ANDREAS KLUWE, LARS LIEBMANN
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	FRANK PREIN ANDREAS KLUWE LARS LIEBMANN
description	In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1208952A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1208952A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1208952A3</originalsourceid><addsrcrecordid>eNrjZLD2TS3JyE9RyE9TKEpNKU3OzEtXyMlPTAHRZYlFmYklmfl5CimlRSCB1JLkDIWCovzk1OJiIJ-HgTUtMac4lRdKczPIu7mGOHvophbkx6cWFyQmp-allsQ7-xkaGVhYmho5GhNWAQAG6C7Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of reducing loading variation during etch processing</title><source>esp@cenet</source><creator>FRANK PREIN ; ANDREAS KLUWE ; LARS LIEBMANN</creator><creatorcontrib>FRANK PREIN ; ANDREAS KLUWE ; LARS LIEBMANN</creatorcontrib><description>In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990224&DB=EPODOC&CC=CN&NR=1208952A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990224&DB=EPODOC&CC=CN&NR=1208952A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FRANK PREIN</creatorcontrib><creatorcontrib>ANDREAS KLUWE</creatorcontrib><creatorcontrib>LARS LIEBMANN</creatorcontrib><title>Method of reducing loading variation during etch processing</title><description>In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD2TS3JyE9RyE9TKEpNKU3OzEtXyMlPTAHRZYlFmYklmfl5CimlRSCB1JLkDIWCovzk1OJiIJ-HgTUtMac4lRdKczPIu7mGOHvophbkx6cWFyQmp-allsQ7-xkaGVhYmho5GhNWAQAG6C7Q</recordid><startdate>19990224</startdate><enddate>19990224</enddate><creator>FRANK PREIN</creator><creator>ANDREAS KLUWE</creator><creator>LARS LIEBMANN</creator><scope>EVB</scope></search><sort><creationdate>19990224</creationdate><title>Method of reducing loading variation during etch processing</title><author>FRANK PREIN ; ANDREAS KLUWE ; LARS LIEBMANN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1208952A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FRANK PREIN</creatorcontrib><creatorcontrib>ANDREAS KLUWE</creatorcontrib><creatorcontrib>LARS LIEBMANN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FRANK PREIN</au><au>ANDREAS KLUWE</au><au>LARS LIEBMANN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of reducing loading variation during etch processing</title><date>1999-02-24</date><risdate>1999</risdate><abstract>In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_CN1208952A
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Method of reducing loading variation during etch processing
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T16%3A32%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FRANK%20PREIN&rft.date=1999-02-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1208952A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true