Semiconductor device with vertical transistor and buried word line
A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word li...
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| creator | JOHAN ALSMEIER THOMAS S. RUPP |
| description | A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN1197161CC</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN1197161CC</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN1197161CC3</originalsourceid><addsrcrecordid>eNqNyjEKAjEQRuE0FqLeYS5gEQTF1qBY2Wi_jDO_OJBNliS7e30RPIDVK763dKc7epOcdJSWCykmE9Bs7U0TSjPhSK1wqla_zknpORaD0pyLUrSEtVu8OFZsfl05upwf4brFkDvUgQUJrQs3748Hv_ch7P5YPh9gMjU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device with vertical transistor and buried word line</title><source>esp@cenet</source><creator>JOHAN ALSMEIER ; THOMAS S. RUPP</creator><creatorcontrib>JOHAN ALSMEIER ; THOMAS S. RUPP</creatorcontrib><description>A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.</description><edition>7</edition><language>eng</language><subject>ELECTRICITY</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050413&DB=EPODOC&CC=CN&NR=1197161C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050413&DB=EPODOC&CC=CN&NR=1197161C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JOHAN ALSMEIER</creatorcontrib><creatorcontrib>THOMAS S. RUPP</creatorcontrib><title>Semiconductor device with vertical transistor and buried word line</title><description>A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKAjEQRuE0FqLeYS5gEQTF1qBY2Wi_jDO_OJBNliS7e30RPIDVK763dKc7epOcdJSWCykmE9Bs7U0TSjPhSK1wqla_zknpORaD0pyLUrSEtVu8OFZsfl05upwf4brFkDvUgQUJrQs3748Hv_ch7P5YPh9gMjU</recordid><startdate>20050413</startdate><enddate>20050413</enddate><creator>JOHAN ALSMEIER</creator><creator>THOMAS S. RUPP</creator><scope>EVB</scope></search><sort><creationdate>20050413</creationdate><title>Semiconductor device with vertical transistor and buried word line</title><author>JOHAN ALSMEIER ; THOMAS S. RUPP</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN1197161CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>JOHAN ALSMEIER</creatorcontrib><creatorcontrib>THOMAS S. RUPP</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JOHAN ALSMEIER</au><au>THOMAS S. RUPP</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device with vertical transistor and buried word line</title><date>2005-04-13</date><risdate>2005</risdate><abstract>A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | ELECTRICITY |
| title | Semiconductor device with vertical transistor and buried word line |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T21%3A31%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JOHAN%20ALSMEIER&rft.date=2005-04-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN1197161CC%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |