Design support system for printed circuit board, design support method, program, and recording medium

This design support system selects and determines a bypass capacitor to be mounted on a substrate from among a plurality of bypass capacitors (C1-C12), and is provided with: a connection path calculation unit (103) that calculates a connection path for all combinations of a plurality of power supply...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KOBAYASHI AKIHITO
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KOBAYASHI AKIHITO
description This design support system selects and determines a bypass capacitor to be mounted on a substrate from among a plurality of bypass capacitors (C1-C12), and is provided with: a connection path calculation unit (103) that calculates a connection path for all combinations of a plurality of power supply terminals (1V) of a semiconductor integrated circuit device and one electrode of the plurality of bypass capacitors (C1-C12); the shortest distance calculation unit calculates the shortest distance in a wiring path from a connection position of a power supply wiring layer to which each of a plurality of power supply terminals (1V) of the semiconductor integrated circuit device (1) is connected to a power supply side wiring layer to which one electrode of each of a plurality of bypass capacitors (C1-C12) is connected. And a validity evaluation unit (104) that, for each of the plurality of power supply terminals, performs a relative comparison of the shortest distances of the wiring paths in the substrates correspon
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118946891A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118946891A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118946891A3</originalsourceid><addsrcrecordid>eNqNiyEPwjAQRmsQBPgPhx-igZBNkgFBofBL6d26JrTXXFvBv2cCg0N9yXvvWyo6U_YuQq4psRTI71wowMgCSXwshGC92OoLPNkINoC_h0Bl4hknYScmNGAigpBlQR_drNHXsFaL0bwybb67Utvr5dHfdpR4oJyMpUhl6O9at93h2Hb6tP-n-QBEmz9j</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Design support system for printed circuit board, design support method, program, and recording medium</title><source>esp@cenet</source><creator>KOBAYASHI AKIHITO</creator><creatorcontrib>KOBAYASHI AKIHITO</creatorcontrib><description>This design support system selects and determines a bypass capacitor to be mounted on a substrate from among a plurality of bypass capacitors (C1-C12), and is provided with: a connection path calculation unit (103) that calculates a connection path for all combinations of a plurality of power supply terminals (1V) of a semiconductor integrated circuit device and one electrode of the plurality of bypass capacitors (C1-C12); the shortest distance calculation unit calculates the shortest distance in a wiring path from a connection position of a power supply wiring layer to which each of a plurality of power supply terminals (1V) of the semiconductor integrated circuit device (1) is connected to a power supply side wiring layer to which one electrode of each of a plurality of bypass capacitors (C1-C12) is connected. And a validity evaluation unit (104) that, for each of the plurality of power supply terminals, performs a relative comparison of the shortest distances of the wiring paths in the substrates correspon</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241112&amp;DB=EPODOC&amp;CC=CN&amp;NR=118946891A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241112&amp;DB=EPODOC&amp;CC=CN&amp;NR=118946891A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOBAYASHI AKIHITO</creatorcontrib><title>Design support system for printed circuit board, design support method, program, and recording medium</title><description>This design support system selects and determines a bypass capacitor to be mounted on a substrate from among a plurality of bypass capacitors (C1-C12), and is provided with: a connection path calculation unit (103) that calculates a connection path for all combinations of a plurality of power supply terminals (1V) of a semiconductor integrated circuit device and one electrode of the plurality of bypass capacitors (C1-C12); the shortest distance calculation unit calculates the shortest distance in a wiring path from a connection position of a power supply wiring layer to which each of a plurality of power supply terminals (1V) of the semiconductor integrated circuit device (1) is connected to a power supply side wiring layer to which one electrode of each of a plurality of bypass capacitors (C1-C12) is connected. And a validity evaluation unit (104) that, for each of the plurality of power supply terminals, performs a relative comparison of the shortest distances of the wiring paths in the substrates correspon</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiyEPwjAQRmsQBPgPhx-igZBNkgFBofBL6d26JrTXXFvBv2cCg0N9yXvvWyo6U_YuQq4psRTI71wowMgCSXwshGC92OoLPNkINoC_h0Bl4hknYScmNGAigpBlQR_drNHXsFaL0bwybb67Utvr5dHfdpR4oJyMpUhl6O9at93h2Hb6tP-n-QBEmz9j</recordid><startdate>20241112</startdate><enddate>20241112</enddate><creator>KOBAYASHI AKIHITO</creator><scope>EVB</scope></search><sort><creationdate>20241112</creationdate><title>Design support system for printed circuit board, design support method, program, and recording medium</title><author>KOBAYASHI AKIHITO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118946891A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KOBAYASHI AKIHITO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOBAYASHI AKIHITO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Design support system for printed circuit board, design support method, program, and recording medium</title><date>2024-11-12</date><risdate>2024</risdate><abstract>This design support system selects and determines a bypass capacitor to be mounted on a substrate from among a plurality of bypass capacitors (C1-C12), and is provided with: a connection path calculation unit (103) that calculates a connection path for all combinations of a plurality of power supply terminals (1V) of a semiconductor integrated circuit device and one electrode of the plurality of bypass capacitors (C1-C12); the shortest distance calculation unit calculates the shortest distance in a wiring path from a connection position of a power supply wiring layer to which each of a plurality of power supply terminals (1V) of the semiconductor integrated circuit device (1) is connected to a power supply side wiring layer to which one electrode of each of a plurality of bypass capacitors (C1-C12) is connected. And a validity evaluation unit (104) that, for each of the plurality of power supply terminals, performs a relative comparison of the shortest distances of the wiring paths in the substrates correspon</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN118946891A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Design support system for printed circuit board, design support method, program, and recording medium
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T09%3A59%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KOBAYASHI%20AKIHITO&rft.date=2024-11-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN118946891A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true