Storage controller and storage device
The invention provides a storage controller and a storage device. The memory controller includes: a host interface configured to communicate with a host; a buffer memory configured to buffer data read from the non-volatile memory; a cache memory including a plurality of cache lines and configured to...
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creator | OH MIN-SIK KIM JONG-MIN EOM KYUNG-SIK DING MINGKUAN KANG DONG-GIL CHO KYOUNG-JUN SONG JIN WOO |
description | The invention provides a storage controller and a storage device. The memory controller includes: a host interface configured to communicate with a host; a buffer memory configured to buffer data read from the non-volatile memory; a cache memory including a plurality of cache lines and configured to store data in at least one of the plurality of cache lines; and a cache controller configured to manage the state bitmap. The status bitmap indicates priority information of the plurality of cache lines in accordance with an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line to be replaced among the plurality of cache lines based on the status bitmap. In this case, an operation corresponding to the request corresponds to one of a normal read, a prefetch, a post-read read, and a post-prefetch read.
提供了一种存储控制器和一种存储设备。所述存储控制器包括:主机接口,被配置为与主机通信;缓冲存储器,被配置为缓冲从非易失性存储器读取的数据;高速缓存存储器,包括多个高速缓存行并且被配置为将数据存储在多个高速缓存行中的至少一者中;以及高速缓存控制器, |
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提供了一种存储控制器和一种存储设备。所述存储控制器包括:主机接口,被配置为与主机通信;缓冲存储器,被配置为缓冲从非易失性存储器读取的数据;高速缓存存储器,包括多个高速缓存行并且被配置为将数据存储在多个高速缓存行中的至少一者中;以及高速缓存控制器,</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240920&DB=EPODOC&CC=CN&NR=118672948A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240920&DB=EPODOC&CC=CN&NR=118672948A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OH MIN-SIK</creatorcontrib><creatorcontrib>KIM JONG-MIN</creatorcontrib><creatorcontrib>EOM KYUNG-SIK</creatorcontrib><creatorcontrib>DING MINGKUAN</creatorcontrib><creatorcontrib>KANG DONG-GIL</creatorcontrib><creatorcontrib>CHO KYOUNG-JUN</creatorcontrib><creatorcontrib>SONG JIN WOO</creatorcontrib><title>Storage controller and storage device</title><description>The invention provides a storage controller and a storage device. The memory controller includes: a host interface configured to communicate with a host; a buffer memory configured to buffer data read from the non-volatile memory; a cache memory including a plurality of cache lines and configured to store data in at least one of the plurality of cache lines; and a cache controller configured to manage the state bitmap. The status bitmap indicates priority information of the plurality of cache lines in accordance with an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line to be replaced among the plurality of cache lines based on the status bitmap. In this case, an operation corresponding to the request corresponds to one of a normal read, a prefetch, a post-read read, and a post-prefetch read.
提供了一种存储控制器和一种存储设备。所述存储控制器包括:主机接口,被配置为与主机通信;缓冲存储器,被配置为缓冲从非易失性存储器读取的数据;高速缓存存储器,包括多个高速缓存行并且被配置为将数据存储在多个高速缓存行中的至少一者中;以及高速缓存控制器,</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFANLskvSkxPVUjOzyspys_JSS1SSMxLUSiGCqeklmUmp_IwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDCzNzI0sTC0djYtQAAE1oJ1k</recordid><startdate>20240920</startdate><enddate>20240920</enddate><creator>OH MIN-SIK</creator><creator>KIM JONG-MIN</creator><creator>EOM KYUNG-SIK</creator><creator>DING MINGKUAN</creator><creator>KANG DONG-GIL</creator><creator>CHO KYOUNG-JUN</creator><creator>SONG JIN WOO</creator><scope>EVB</scope></search><sort><creationdate>20240920</creationdate><title>Storage controller and storage device</title><author>OH MIN-SIK ; KIM JONG-MIN ; EOM KYUNG-SIK ; DING MINGKUAN ; KANG DONG-GIL ; CHO KYOUNG-JUN ; SONG JIN WOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118672948A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OH MIN-SIK</creatorcontrib><creatorcontrib>KIM JONG-MIN</creatorcontrib><creatorcontrib>EOM KYUNG-SIK</creatorcontrib><creatorcontrib>DING MINGKUAN</creatorcontrib><creatorcontrib>KANG DONG-GIL</creatorcontrib><creatorcontrib>CHO KYOUNG-JUN</creatorcontrib><creatorcontrib>SONG JIN WOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OH MIN-SIK</au><au>KIM JONG-MIN</au><au>EOM KYUNG-SIK</au><au>DING MINGKUAN</au><au>KANG DONG-GIL</au><au>CHO KYOUNG-JUN</au><au>SONG JIN WOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Storage controller and storage device</title><date>2024-09-20</date><risdate>2024</risdate><abstract>The invention provides a storage controller and a storage device. The memory controller includes: a host interface configured to communicate with a host; a buffer memory configured to buffer data read from the non-volatile memory; a cache memory including a plurality of cache lines and configured to store data in at least one of the plurality of cache lines; and a cache controller configured to manage the state bitmap. The status bitmap indicates priority information of the plurality of cache lines in accordance with an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line to be replaced among the plurality of cache lines based on the status bitmap. In this case, an operation corresponding to the request corresponds to one of a normal read, a prefetch, a post-read read, and a post-prefetch read.
提供了一种存储控制器和一种存储设备。所述存储控制器包括:主机接口,被配置为与主机通信;缓冲存储器,被配置为缓冲从非易失性存储器读取的数据;高速缓存存储器,包括多个高速缓存行并且被配置为将数据存储在多个高速缓存行中的至少一者中;以及高速缓存控制器,</abstract><oa>free_for_read</oa></addata></record> |
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language | chi ; eng |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Storage controller and storage device |
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