Semiconductor device and preparation method thereof
The invention provides a semiconductor device, a first dielectric layer is arranged on a substrate, a plurality of mutually separated first conductive patterns and a barrier layer are arranged in the first dielectric layer, the barrier layer is located on the first conductive patterns, and at least...
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| creator | HUANG JIANBIN LIU ANQI DING JIAGENG ZHU AYUAN CHEN SUNHONG LIN YUCHUN XIE CHAOJING WENG QIAOHANG |
| description | The invention provides a semiconductor device, a first dielectric layer is arranged on a substrate, a plurality of mutually separated first conductive patterns and a barrier layer are arranged in the first dielectric layer, the barrier layer is located on the first conductive patterns, and at least part of the top surface of the barrier layer is exposed out of the first dielectric layer; the metal oxide layer is located on the first dielectric layer and the barrier layer, the second dielectric layer is located on the metal oxide layer, and the multiple conductive columns are arranged in the second dielectric layer in a mutually separated mode and penetrate through the metal oxide layer to make contact with the barrier layer so as to be electrically connected with the first conductive pattern through the barrier layer. The blocking layer can block the metal oxide layer and the first conductive pattern, after the metal oxide layer is formed, the metal oxide layer does not make contact with the first conductive |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN118610191A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN118610191A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN118610191A3</originalsourceid><addsrcrecordid>eNrjZDAOTs3NTM7PSylNLskvUkhJLctMTlVIzEtRKChKLUgsSizJzM9TyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhhZmhgaGloaOxsSoAQArLCzH</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and preparation method thereof</title><source>esp@cenet</source><creator>HUANG JIANBIN ; LIU ANQI ; DING JIAGENG ; ZHU AYUAN ; CHEN SUNHONG ; LIN YUCHUN ; XIE CHAOJING ; WENG QIAOHANG</creator><creatorcontrib>HUANG JIANBIN ; LIU ANQI ; DING JIAGENG ; ZHU AYUAN ; CHEN SUNHONG ; LIN YUCHUN ; XIE CHAOJING ; WENG QIAOHANG</creatorcontrib><description>The invention provides a semiconductor device, a first dielectric layer is arranged on a substrate, a plurality of mutually separated first conductive patterns and a barrier layer are arranged in the first dielectric layer, the barrier layer is located on the first conductive patterns, and at least part of the top surface of the barrier layer is exposed out of the first dielectric layer; the metal oxide layer is located on the first dielectric layer and the barrier layer, the second dielectric layer is located on the metal oxide layer, and the multiple conductive columns are arranged in the second dielectric layer in a mutually separated mode and penetrate through the metal oxide layer to make contact with the barrier layer so as to be electrically connected with the first conductive pattern through the barrier layer. The blocking layer can block the metal oxide layer and the first conductive pattern, after the metal oxide layer is formed, the metal oxide layer does not make contact with the first conductive</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240906&DB=EPODOC&CC=CN&NR=118610191A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240906&DB=EPODOC&CC=CN&NR=118610191A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HUANG JIANBIN</creatorcontrib><creatorcontrib>LIU ANQI</creatorcontrib><creatorcontrib>DING JIAGENG</creatorcontrib><creatorcontrib>ZHU AYUAN</creatorcontrib><creatorcontrib>CHEN SUNHONG</creatorcontrib><creatorcontrib>LIN YUCHUN</creatorcontrib><creatorcontrib>XIE CHAOJING</creatorcontrib><creatorcontrib>WENG QIAOHANG</creatorcontrib><title>Semiconductor device and preparation method thereof</title><description>The invention provides a semiconductor device, a first dielectric layer is arranged on a substrate, a plurality of mutually separated first conductive patterns and a barrier layer are arranged in the first dielectric layer, the barrier layer is located on the first conductive patterns, and at least part of the top surface of the barrier layer is exposed out of the first dielectric layer; the metal oxide layer is located on the first dielectric layer and the barrier layer, the second dielectric layer is located on the metal oxide layer, and the multiple conductive columns are arranged in the second dielectric layer in a mutually separated mode and penetrate through the metal oxide layer to make contact with the barrier layer so as to be electrically connected with the first conductive pattern through the barrier layer. The blocking layer can block the metal oxide layer and the first conductive pattern, after the metal oxide layer is formed, the metal oxide layer does not make contact with the first conductive</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAOTs3NTM7PSylNLskvUkhJLctMTlVIzEtRKChKLUgsSizJzM9TyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhhZmhgaGloaOxsSoAQArLCzH</recordid><startdate>20240906</startdate><enddate>20240906</enddate><creator>HUANG JIANBIN</creator><creator>LIU ANQI</creator><creator>DING JIAGENG</creator><creator>ZHU AYUAN</creator><creator>CHEN SUNHONG</creator><creator>LIN YUCHUN</creator><creator>XIE CHAOJING</creator><creator>WENG QIAOHANG</creator><scope>EVB</scope></search><sort><creationdate>20240906</creationdate><title>Semiconductor device and preparation method thereof</title><author>HUANG JIANBIN ; LIU ANQI ; DING JIAGENG ; ZHU AYUAN ; CHEN SUNHONG ; LIN YUCHUN ; XIE CHAOJING ; WENG QIAOHANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118610191A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HUANG JIANBIN</creatorcontrib><creatorcontrib>LIU ANQI</creatorcontrib><creatorcontrib>DING JIAGENG</creatorcontrib><creatorcontrib>ZHU AYUAN</creatorcontrib><creatorcontrib>CHEN SUNHONG</creatorcontrib><creatorcontrib>LIN YUCHUN</creatorcontrib><creatorcontrib>XIE CHAOJING</creatorcontrib><creatorcontrib>WENG QIAOHANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HUANG JIANBIN</au><au>LIU ANQI</au><au>DING JIAGENG</au><au>ZHU AYUAN</au><au>CHEN SUNHONG</au><au>LIN YUCHUN</au><au>XIE CHAOJING</au><au>WENG QIAOHANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and preparation method thereof</title><date>2024-09-06</date><risdate>2024</risdate><abstract>The invention provides a semiconductor device, a first dielectric layer is arranged on a substrate, a plurality of mutually separated first conductive patterns and a barrier layer are arranged in the first dielectric layer, the barrier layer is located on the first conductive patterns, and at least part of the top surface of the barrier layer is exposed out of the first dielectric layer; the metal oxide layer is located on the first dielectric layer and the barrier layer, the second dielectric layer is located on the metal oxide layer, and the multiple conductive columns are arranged in the second dielectric layer in a mutually separated mode and penetrate through the metal oxide layer to make contact with the barrier layer so as to be electrically connected with the first conductive pattern through the barrier layer. The blocking layer can block the metal oxide layer and the first conductive pattern, after the metal oxide layer is formed, the metal oxide layer does not make contact with the first conductive</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor device and preparation method thereof |
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