Preparation method of semiconductor structure, semiconductor structure and memory

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate which is provided with an array region, a transition region surrounding the array region, and a peripheral...

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description The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate which is provided with an array region, a transition region surrounding the array region, and a peripheral region surrounding the transition region; forming a stacked layer on the substrate, wherein the stacked layer comprises a conductive material layer located on the substrate; removing the stacking layer in the transition region to form a first groove; forming a first isolation structure in the first groove, wherein the conductive material layer in the array region is electrically isolated from the conductive material layer in the peripheral region through the first isolation structure; a first mask pattern is formed, the first mask pattern comprises two parallel strip-shaped main body parts and a bending part connected with the two strip-shaped main body parts, the two strip-shaped main body parts are at least loca
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forming a stacked layer on the substrate, wherein the stacked layer comprises a conductive material layer located on the substrate; removing the stacking layer in the transition region to form a first groove; forming a first isolation structure in the first groove, wherein the conductive material layer in the array region is electrically isolated from the conductive material layer in the peripheral region through the first isolation structure; a first mask pattern is formed, the first mask pattern comprises two parallel strip-shaped main body parts and a bending part connected with the two strip-shaped main body parts, the two strip-shaped main body parts are at least loca</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240820&amp;DB=EPODOC&amp;CC=CN&amp;NR=118524699A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240820&amp;DB=EPODOC&amp;CC=CN&amp;NR=118524699A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BAO XIFEI</creatorcontrib><title>Preparation method of semiconductor structure, semiconductor structure and memory</title><description>The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate which is provided with an array region, a transition region surrounding the array region, and a peripheral region surrounding the transition region; forming a stacked layer on the substrate, wherein the stacked layer comprises a conductive material layer located on the substrate; removing the stacking layer in the transition region to form a first groove; forming a first isolation structure in the first groove, wherein the conductive material layer in the array region is electrically isolated from the conductive material layer in the peripheral region through the first isolation structure; a first mask pattern is formed, the first mask pattern comprises two parallel strip-shaped main body parts and a bending part connected with the two strip-shaped main body parts, the two strip-shaped main body parts are at least loca</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgMKEotSCxKLMnMz1PITS3JyE9RyE9TKE7NzUzOz0spTS7JL1IoLikCMkqLUnVwSSgk5qUAtefmF1XyMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz9DQwtTIxMzS0tHY2LUAAB3lzkF</recordid><startdate>20240820</startdate><enddate>20240820</enddate><creator>BAO XIFEI</creator><scope>EVB</scope></search><sort><creationdate>20240820</creationdate><title>Preparation method of semiconductor structure, semiconductor structure and memory</title><author>BAO XIFEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118524699A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; 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title Preparation method of semiconductor structure, semiconductor structure and memory
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