Multi-topology networking and high-speed data synchronization system for PLC (Programmable Logic Controller)
The invention provides a PLC controller multi-topology networking and high-speed data synchronization system, and relates to the technical field of controllers, the PLC controller multi-topology networking and high-speed data synchronization system comprises a plurality of single/double-path RapidIO...
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| creator | ZHU JIANWEN QIN KAIYUN MENG XIANGMING |
| description | The invention provides a PLC controller multi-topology networking and high-speed data synchronization system, and relates to the technical field of controllers, the PLC controller multi-topology networking and high-speed data synchronization system comprises a plurality of single/double-path RapidIO industrial controllers, and the single/double-path RapidIO industrial controllers are connected through a plurality of links; the single/double RapidIO industrial controller comprises a CPU (Central Processing Unit) processor unit, an RAM (Random Access Memory) unit, an ROM (Read Only Memory) unit, a power supply unit, an input unit, an output unit, a high-speed data processing unit and an interface unit, the RAM unit, the ROM unit and the power supply unit are respectively connected to the CPU processor unit, and the CPU processor unit is respectively connected to the input unit, the output unit and the high-speed data processing unit; the input unit, the output unit and the high-speed data processing unit are re |
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the single/double RapidIO industrial controller comprises a CPU (Central Processing Unit) processor unit, an RAM (Random Access Memory) unit, an ROM (Read Only Memory) unit, a power supply unit, an input unit, an output unit, a high-speed data processing unit and an interface unit, the RAM unit, the ROM unit and the power supply unit are respectively connected to the CPU processor unit, and the CPU processor unit is respectively connected to the input unit, the output unit and the high-speed data processing unit; the input unit, the output unit and the high-speed data processing unit are re</description><language>chi ; eng</language><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; REGULATING ; SELECTING ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240820&DB=EPODOC&CC=CN&NR=118524314A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240820&DB=EPODOC&CC=CN&NR=118524314A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHU JIANWEN</creatorcontrib><creatorcontrib>QIN KAIYUN</creatorcontrib><creatorcontrib>MENG XIANGMING</creatorcontrib><title>Multi-topology networking and high-speed data synchronization system for PLC (Programmable Logic Controller)</title><description>The invention provides a PLC controller multi-topology networking and high-speed data synchronization system, and relates to the technical field of controllers, the PLC controller multi-topology networking and high-speed data synchronization system comprises a plurality of single/double-path RapidIO industrial controllers, and the single/double-path RapidIO industrial controllers are connected through a plurality of links; the single/double RapidIO industrial controller comprises a CPU (Central Processing Unit) processor unit, an RAM (Random Access Memory) unit, an ROM (Read Only Memory) unit, a power supply unit, an input unit, an output unit, a high-speed data processing unit and an interface unit, the RAM unit, the ROM unit and the power supply unit are respectively connected to the CPU processor unit, and the CPU processor unit is respectively connected to the input unit, the output unit and the high-speed data processing unit; the input unit, the output unit and the high-speed data processing unit are re</description><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SELECTING</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbEKwjAQQLs4iPoP56ZDh9oKrhIUhyod3MvZXtNgeheSiNSvt4Mf4PR48ODNE3t92WjSKE6s6BGY4lv807AG5BZ6o_s0OKIWWowIYeSm98Lmg9EITx4iDdCJh6pUsKm8aI_DgA9LUIo2DSjh6MVa8ttlMuvQBlr9uEjW59NdXVJyUlNw2ND0r9Utyw77XZFnxTH_p_kCTN9Bzg</recordid><startdate>20240820</startdate><enddate>20240820</enddate><creator>ZHU JIANWEN</creator><creator>QIN KAIYUN</creator><creator>MENG XIANGMING</creator><scope>EVB</scope></search><sort><creationdate>20240820</creationdate><title>Multi-topology networking and high-speed data synchronization system for PLC (Programmable Logic Controller)</title><author>ZHU JIANWEN ; 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the single/double RapidIO industrial controller comprises a CPU (Central Processing Unit) processor unit, an RAM (Random Access Memory) unit, an ROM (Read Only Memory) unit, a power supply unit, an input unit, an output unit, a high-speed data processing unit and an interface unit, the RAM unit, the ROM unit and the power supply unit are respectively connected to the CPU processor unit, and the CPU processor unit is respectively connected to the input unit, the output unit and the high-speed data processing unit; the input unit, the output unit and the high-speed data processing unit are re</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING SELECTING TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | Multi-topology networking and high-speed data synchronization system for PLC (Programmable Logic Controller) |
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